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[Qemu-devel] [PATCH 3/6] target-ppc: POWER7+ supports the MSR_VSX bit
From: |
Anton Blanchard |
Subject: |
[Qemu-devel] [PATCH 3/6] target-ppc: POWER7+ supports the MSR_VSX bit |
Date: |
Tue, 25 Mar 2014 13:40:28 +1100 |
Without MSR_VSX we die early during a Linux boot.
Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4fda0fd..87c00a1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7118,7 +7118,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206;
- pcc->msr_mask = 0x800000000204FF37ULL;
+ pcc->msr_mask = 0x800000000284FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
--
1.8.3.2
- [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit, Anton Blanchard, 2014/03/24
- [Qemu-devel] [PATCH 2/6] target-ppc: POWER8 supports isel, Anton Blanchard, 2014/03/24
- [Qemu-devel] [PATCH 5/6] target-ppc: Fix Book3S PMU SPRs, Anton Blanchard, 2014/03/24
- [Qemu-devel] [PATCH 4/6] target-ppc: MSR_POW not supported on POWER7/7+/8, Anton Blanchard, 2014/03/24
- [Qemu-devel] [PATCH 6/6] target-ppc: Add PMC7/8 to 970, Anton Blanchard, 2014/03/24
- [Qemu-devel] [PATCH 3/6] target-ppc: POWER7+ supports the MSR_VSX bit,
Anton Blanchard <=
- Re: [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit, Alex Bennée, 2014/03/25
- Re: [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit, Andreas Färber, 2014/03/27