Re: [Qemu-devel] [PATCH v3 0/3] ARM pl011 fixes

[Peter Maydell]

On 18 March 2014 18:18, Rob Herring <address@hidden> wrote:
> From: Rob Herring <address@hidden>
>
> Intermittent issues have been seen where no serial input occurs. It
> appears the pl011 gets in a state where the rx interrupt never fires
> because the rx interrupt only asserts when crossing the fifo trigger
> level. The fifo state appears to get out of sync when the pl011 is
> re-configured. This combined with the rx timeout interrupt not being
> modeled results in no more rx interrupts.
>
> This problem is fixed by the 1st patch. The 2 other patches are problems
> I noticed while debugging this issue. They are more for correctness of
> the model than fixing any observed issues.
>
> Changes in v3:
> - Fix logic for checking if FIFO enable bit has changed
> - Add vmstate for UARTRSR register
> - Dropped patch 4

Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM