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[Qemu-devel] [PULL 17/30] target-arm: A64: List unsupported shift-imm op
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/30] target-arm: A64: List unsupported shift-imm opcodes |
Date: |
Mon, 17 Mar 2014 22:12:08 +0000 |
Add the remaining unsupported opcodes to the decode switches
for the shift-imm and scalar shift-imm categories so we can
see what is still to be implemented.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target-arm/translate-a64.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index e6addf4..2b1ca64 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -6135,9 +6135,15 @@ static void disas_simd_scalar_shift_imm(DisasContext *s,
uint32_t insn)
handle_vec_simd_sqshrn(s, true, false, is_u, is_u,
immh, immb, opcode, rn, rd);
break;
- default:
+ case 0x8: /* SRI */
+ case 0xc: /* SQSHLU */
+ case 0xe: /* SQSHL, UQSHL */
+ case 0x1f: /* FCVTZS, FCVTZU */
unsupported_encoding(s, insn);
break;
+ default:
+ unallocated_encoding(s);
+ break;
}
}
@@ -7281,11 +7287,14 @@ static void disas_simd_shift_imm(DisasContext *s,
uint32_t insn)
handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
opcode, rn, rd);
break;
+ case 0x8: /* SRI */
+ case 0xc: /* SQSHLU */
+ case 0xe: /* SQSHL, UQSHL */
case 0x1f: /* FCVTZS/ FCVTZU */
unsupported_encoding(s, insn);
return;
default:
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
return;
}
}
--
1.9.0
- [Qemu-devel] [PULL for-2.0rc1 00/30] target-arm queue, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 12/30] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 10/30] target-arm: A64: Add remaining CLS/Z vector ops, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 23/30] target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 17/30] target-arm: A64: List unsupported shift-imm opcodes,
Peter Maydell <=
- [Qemu-devel] [PULL 27/30] target-arm: A64: Implement scalar saturating narrow ops, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 30/30] scripts/qemu-binfmt-conf.sh: Add AArch64 registration, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 11/30] target-arm: A64: Saturating and narrowing shift ops, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 20/30] target-arm: A64: Implement FRINT*, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 29/30] target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate), Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 15/30] target-arm: A64: Implement FCVTN, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 08/30] target-arm: A64: Add last AdvSIMD Integer to FP ops, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 24/30] softfloat: export squash_input_denormal functions, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 01/30] vexpress: Set reset-cbar property for CPUs, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 18/30] target-arm: A64: Add FRECPX (reciprocal exponent), Peter Maydell, 2014/03/17