qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU


From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
Date: Tue, 11 Mar 2014 13:53:46 +0000

On 9 March 2014 15:11, Peter Maydell <address@hidden> wrote:
> Implement the floating-point-to-integer conversion instructions
> FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc
> categories.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> @@ -8573,6 +8657,11 @@ static void disas_simd_two_reg_misc(DisasContext *s, 
> uint32_t insn)
>      bool is_q = extract32(insn, 30, 1);
>      int rn = extract32(insn, 5, 5);
>      int rd = extract32(insn, 0, 5);
> +    bool need_fpstatus = false;
> +    bool need_rmode = false;
> +    int rmode;

This needs to be "int rmode = -1;" since some versions
of gcc otherwise complain about maybe-used-uninitialized
(not actually true since on all code paths we set rmode
if setting need_rmode to true, and only use rmode if
need_rmode is set).

No idea why only this function and not the scalar_two_reg_misc
similar construct provokes the warning....

thanks
-- PMM



reply via email to

[Prev in Thread] Current Thread [Next in Thread]