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[Qemu-devel] [PULL 041/130] target-ppc: VSX Stage 4: Add xsdivsp
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 041/130] target-ppc: VSX Stage 4: Add xsdivsp |
Date: |
Fri, 7 Mar 2014 00:32:48 +0100 |
From: Tom Musta <address@hidden>
This patch adds the VSX Scalar Divide Single Precision (xsdivsp)
instruction.
The existing VSX_DIV macro is modified to support rounding of the
intermediate double precision result to single precision.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/fpu_helper.c | 13 +++++++++----
target-ppc/helper.h | 1 +
target-ppc/translate.c | 2 ++
3 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index dc9849f..49cf09a 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1874,7 +1874,7 @@ VSX_MUL(xvmulsp, 4, float32, f32, 0, 0)
* fld - vsr_t field (f32 or f64)
* sfprf - set FPRF
*/
-#define VSX_DIV(op, nels, tp, fld, sfprf) \
+#define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
ppc_vsr_t xt, xa, xb; \
@@ -1903,6 +1903,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
} \
} \
\
+ if (r2sp) { \
+ xt.fld[i] = helper_frsp(env, xt.fld[i]); \
+ } \
+ \
if (sfprf) { \
helper_compute_fprf(env, xt.fld[i], sfprf); \
} \
@@ -1912,9 +1916,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
helper_float_check_status(env); \
}
-VSX_DIV(xsdivdp, 1, float64, f64, 1)
-VSX_DIV(xvdivdp, 2, float64, f64, 0)
-VSX_DIV(xvdivsp, 4, float32, f32, 0)
+VSX_DIV(xsdivdp, 1, float64, f64, 1, 0)
+VSX_DIV(xsdivsp, 1, float64, f64, 1, 1)
+VSX_DIV(xvdivdp, 2, float64, f64, 0, 0)
+VSX_DIV(xvdivsp, 4, float32, f32, 0, 0)
/* VSX_RE - VSX floating point reciprocal estimate
* op - instruction mnemonic
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0ccdc96..308f97c 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -289,6 +289,7 @@ DEF_HELPER_2(xsrdpiz, void, env, i32)
DEF_HELPER_2(xsaddsp, void, env, i32)
DEF_HELPER_2(xssubsp, void, env, i32)
DEF_HELPER_2(xsmulsp, void, env, i32)
+DEF_HELPER_2(xsdivsp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 87817c2..dd4ddad 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7361,6 +7361,7 @@ GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -10171,6 +10172,7 @@ GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
+GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
--
1.8.1.4
- [Qemu-devel] [PULL 037/130] target-ppc: VSX Stage 4: Refactor stxsdx, (continued)
- [Qemu-devel] [PULL 037/130] target-ppc: VSX Stage 4: Refactor stxsdx, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 038/130] target-ppc: VSX Stage 4: Add stxsiwx and stxsspx, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 039/130] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 033/130] target-ppc: Add VSX Rounding Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 040/130] target-ppc: VSX Stage 4: Add xsmulsp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 028/130] target-ppc: Add VSX xscmp*dp Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 042/130] target-ppc: VSX Stage 4: Add xsresp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 022/130] target-ppc: Add VSX ISA2.06 xre Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 045/130] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 030/130] target-ppc: Add VSX Vector Compare Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 041/130] target-ppc: VSX Stage 4: Add xsdivsp,
Alexander Graf <=
- [Qemu-devel] [PULL 047/130] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 049/130] target-ppc: Floating Merge Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 043/130] target-ppc: VSX Stage 4: Add xssqrtsp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 046/130] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 056/130] target-ppc: Add ISA 2.06 divweu[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 053/130] target-ppc: Add Flag for ISA2.06 Divide Extended Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 057/130] target-ppc: Add ISA 2.06 divwe[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 050/130] target-ppc: Scalar Round to Single Precision, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 048/130] target-ppc: Move To/From VSR Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 044/130] target-ppc: VSX Stage 4: add xsrsqrtesp, Alexander Graf, 2014/03/06