[Qemu-devel] [PATCH v4 00/21] AArch64 system emulation (boots a kernel!)

[Peter Maydell]

This is v4 of the AArch64 system emulation patches, and it's
an important milestone -- this is enough to boot a Linux kernel.

Changes v3->v4:
 * reviewed patches from bottom of stack got committed to master
 * new patches at top of stack
 * addressed review issues on v8 mmu translation patch and DAIF patch

RTH: you'll probably be interested in reviewing the DC ZVA patch,
 and maybe also the syndrome info/FP fault/VFP enable patches.

This patchset owes much more to Rob Herring than the raw patch
authorship stats would suggest -- he did all the "get the thing
actually booting" work and tracked down some nasty "intermittent
hang" bugs. I did most of the syndrome related bits and some
cleanup work.

Apart from the slightly questionable use of a15mpcore_priv
in the virt patch at the end, I'm generally happy with this code.
It'll have to wait for end of hardfreeze, though.

Possible "bugfix" candidates from here would be the ARM946
patch, and implementing DC ZVA (this is a huge speedup on
linux-user code if the guest makes much use of it at all).
We also fix a problem with handling of SP in KVM AArch64,
which will be noticeable if trying to use gdb. (This is
the one Claudio reported.)

thanks
-- PMM

Peter Maydell (17):
  target-arm: Split out private-to-target functions into internals.h
  target-arm: Implement AArch64 DAIF system register
  target-arm: Define exception record for AArch64 exceptions
  target-arm: Provide correct syndrome information for cpreg access
    traps
  target-arm: Add support for generating exceptions with syndrome
    information
  target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
  target-arm: A64: Add assertion that FP access was checked
  target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1
  target-arm: Don't mention PMU in debug feature register
  target-arm: A64: Implement DC ZVA
  target-arm: Use dedicated CPU state fields for ARM946 access bit
    registers
  target-arm: Add AArch64 ELR_EL1 register.
  target-arm: Implement SP_EL0, SP_EL1
  target-arm: Implement AArch64 SPSR_EL1
  target-arm: Move arm_log_exception() into internals.h
  target-arm: Add Cortex-A57 processor
  hw/arm/virt: Add support for Cortex-A57

Rob Herring (4):
  target-arm: Provide syndrome information for MMU faults
  target-arm: Add v8 mmu translation support
  target-arm: Implement AArch64 views of fault status and data registers
  target-arm: Implement AArch64 EL1 exception handling

 hw/arm/virt.c               |   8 +
 include/exec/softmmu_exec.h |  36 ++++
 linux-user/main.c           |  56 +++---
 target-arm/cpu-qom.h        |   4 +
 target-arm/cpu.c            |  10 +-
 target-arm/cpu.h            |  74 +++++---
 target-arm/cpu64.c          |  45 +++++
 target-arm/helper-a64.c     |  75 ++++++++
 target-arm/helper.c         | 419 ++++++++++++++++++++++++++++++++++----------
 target-arm/helper.h         |   7 +-
 target-arm/internals.h      | 267 ++++++++++++++++++++++++++++
 target-arm/kvm32.c          |  19 +-
 target-arm/kvm64.c          |  71 +++++++-
 target-arm/machine.c        |  13 +-
 target-arm/op_helper.c      |  90 +++++++++-
 target-arm/translate-a64.c  | 383 +++++++++++++++++++++++++++++++++++-----
 target-arm/translate.c      | 168 +++++++++++++-----
 target-arm/translate.h      |  15 +-
 18 files changed, 1499 insertions(+), 261 deletions(-)
 create mode 100644 target-arm/internals.h

-- 
1.9.0