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[Qemu-devel] [PULL 22/45] target-arm: Implement AArch64 SCTLR_EL1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/45] target-arm: Implement AArch64 SCTLR_EL1 |
Date: |
Wed, 26 Feb 2014 18:02:12 +0000 |
Implement the AArch64 view of the system control register SCTLR_EL1.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/cpu.h | 2 +-
target-arm/helper.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 51fa634..74b1122 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -169,7 +169,7 @@ typedef struct CPUARMState {
struct {
uint32_t c0_cpuid;
uint64_t c0_cssel; /* Cache size selection. */
- uint32_t c1_sys; /* System control register. */
+ uint64_t c1_sys; /* System control register. */
uint32_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint32_t c1_scr; /* secure config register. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e230a18..630ace9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1948,7 +1948,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
/* Generic registers whose values depend on the implementation */
{
ARMCPRegInfo sctlr = {
- .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 =
0,
+ .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState,
cp15.c1_sys),
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
.raw_writefn = raw_write,
--
1.9.0
- [Qemu-devel] [PULL 40/45] dma/pl330: Fix misleading type, (continued)
- [Qemu-devel] [PULL 40/45] dma/pl330: Fix misleading type, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 39/45] dma/pl330: Delete overly verbose debug printf, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 41/45] dma/pl330: printf format type sweep., Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 12/45] arm: vgic device control api support, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 23/45] target-arm: Implement AArch64 TCR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 37/45] include/qemu/crc32c.h: Rename include guards to match filename, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 36/45] target-arm: Add utility function for checking AA32/64 state of an EL, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 38/45] target-arm: Add support for AArch32 ARMv8 CRC32 instructions, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 44/45] dma/pl330: Fix buffer depth, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 35/45] target-arm: Implement AArch64 view of CPACR, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 22/45] target-arm: Implement AArch64 SCTLR_EL1,
Peter Maydell <=
- [Qemu-devel] [PULL 31/45] target-arm: Get MMU index information correct for A64 code, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 04/45] target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 24/45] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 33/45] target-arm: Store AIF bits in env->pstate for AArch32, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 17/45] target-arm: Implement AArch64 MIDR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 27/45] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 30/45] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 29/45] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 34/45] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 15/45] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/02/26