Re: [Qemu-devel] [PATCH v3 12/31] target-arm: Implement AArch64 TTBR*

[Peter Maydell]

On 26 February 2014 06:33, Hu Tao <address@hidden> wrote:
> On Sat, Feb 15, 2014 at 04:07:05PM +0000, Peter Maydell wrote:
>
> <...>
>
>> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
>> index 06953ac..7cbe69b 100644
>> --- a/target-arm/cpu.h
>> +++ b/target-arm/cpu.h
>> @@ -173,10 +173,8 @@ typedef struct CPUARMState {
>>          uint32_t c1_coproc; /* Coprocessor access register.  */
>>          uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
>>          uint32_t c1_scr; /* secure config register.  */
>> -        uint32_t c2_base0; /* MMU translation table base 0.  */
>> -        uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits 
>> */
>> -        uint32_t c2_base1; /* MMU translation table base 0.  */
>> -        uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits 
>> */
>> +        uint64_t ttbr0_el1; /* MMU translation table base 0. */
>> +        uint32_t ttbr1_el1; /* MMU translation table base 1. */
>
> s/32/64/

Nice catch, not sure how I missed that.

thanks
-- PMM