[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 12/15] tcg/i386: Move TCG_CT_CONST_* to tcg-target.c
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 12/15] tcg/i386: Move TCG_CT_CONST_* to tcg-target.c |
Date: |
Mon, 17 Feb 2014 19:16:02 -0600 |
These are not needed by users of tcg-target.h. No need to recompile
when we adjust them.
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/i386/tcg-target.c | 4 ++++
tcg/i386/tcg-target.h | 3 ---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 5d4cf93..7008b0e 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -88,6 +88,10 @@ static const int tcg_target_call_oarg_regs[] = {
#endif
};
+/* Constants we accept. */
+#define TCG_CT_CONST_S32 0x100
+#define TCG_CT_CONST_U32 0x200
+
/* Registers used with L constraint, which are the first argument
registers on x86_64, and two random call clobbered registers on
i386. */
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 92c0fcd..747b797 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -64,9 +64,6 @@ typedef enum {
TCG_REG_RDI = TCG_REG_EDI,
} TCGReg;
-#define TCG_CT_CONST_S32 0x100
-#define TCG_CT_CONST_U32 0x200
-
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_ESP
#define TCG_TARGET_STACK_ALIGN 16
--
1.8.5.3
- [Qemu-devel] [PULL 01/15] TCG: Fix 32-bit host allocation typo, (continued)
- [Qemu-devel] [PULL 01/15] TCG: Fix 32-bit host allocation typo, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 03/15] tcg/optimize: fix known-zero bits for right shift ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 04/15] tcg/optimize: fix known-zero bits optimization, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 05/15] tcg/optimize: improve known-zero bits for 32-bit ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 06/15] tcg/optimize: add known-zero bits compute for load ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 07/15] tcg/optimize: Handle known-zeros masks for ANDC, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 08/15] tcg/optimize: Simply some logical ops to NOT, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 09/15] tcg/optimize: Optmize ANDC X, Y, Y to MOV X, 0, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 10/15] tcg/optimize: Add more identity simplifications, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 11/15] disas/i386: Disassemble ANDN/SHLX/SHRX/SHAX, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 12/15] tcg/i386: Move TCG_CT_CONST_* to tcg-target.c,
Richard Henderson <=
- [Qemu-devel] [PULL 13/15] tcg/i386: Add tcg_out_vex_modrm, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 15/15] tcg/i386: Use SHLX/SHRX/SARX instructions, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 14/15] tcg/i386: Use ANDN instruction, Richard Henderson, 2014/02/17
- Re: [Qemu-devel] [PULL 00/15] tcg updates, Kevin Wolf, 2014/02/19
- Re: [Qemu-devel] [PULL 00/15] tcg updates, Peter Maydell, 2014/02/20