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[Qemu-devel] [PATCH 22/28] target-ppc: Altivec 2.07: Doubleword Compares
From: |
Tom Musta |
Subject: |
[Qemu-devel] [PATCH 22/28] target-ppc: Altivec 2.07: Doubleword Compares |
Date: |
Wed, 12 Feb 2014 15:23:13 -0600 |
This patch adds the Vector Compare Doubleword instructions introduced
by Power ISA Version 2.07:
- Vector Compare Equal to Unsigned Doubleword (vcmpequd)
- Vector Compare Greater Than Signed Doubleword (vcmpgtsd)
- Vector Compare Greater Than Unsigned Doubleword (vcmpgtud)
These instructions are encoded with bit 31 set to 1 and so are duals with
vcmpeqfp, vcmpgtfp and vcmpbfp respectively.
The helper macro for integer compares is enhanced to account for 64-bit
operands.
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/helper.h | 6 ++++++
target-ppc/int_helper.c | 14 ++++++++++----
target-ppc/translate.c | 16 +++++++++++++---
3 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index ca1dc83..9613654 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -139,12 +139,15 @@ DEF_HELPER_3(vmaxud, void, avr, avr, avr)
DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpequd, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtub, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuw, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpgtud, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsb, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsw, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpgtsd, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpeqfp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgefp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtfp, void, env, avr, avr, avr)
@@ -152,12 +155,15 @@ DEF_HELPER_4(vcmpbfp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequb_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequw_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpequd_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtub_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuw_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpgtud_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsb_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsw_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpgtsd_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 5885b7e..27a34c0 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -626,15 +626,18 @@ VCF(sx, int32_to_float32, s32)
void helper_vcmp##suffix(CPUPPCState *env, ppc_avr_t *r, \
ppc_avr_t *a, ppc_avr_t *b) \
{ \
- uint32_t ones = (uint32_t)-1; \
- uint32_t all = ones; \
- uint32_t none = 0; \
+ uint64_t ones = (uint64_t)-1; \
+ uint64_t all = ones; \
+ uint64_t none = 0; \
int i; \
\
for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- uint32_t result = (a->element[i] compare b->element[i] ? \
+ uint64_t result = (a->element[i] compare b->element[i] ? \
ones : 0x0); \
switch (sizeof(a->element[0])) { \
+ case 8: \
+ r->u64[i] = result; \
+ break; \
case 4: \
r->u32[i] = result; \
break; \
@@ -658,12 +661,15 @@ VCF(sx, int32_to_float32, s32)
VCMP(equb, ==, u8)
VCMP(equh, ==, u16)
VCMP(equw, ==, u32)
+VCMP(equd, ==, u64)
VCMP(gtub, >, u8)
VCMP(gtuh, >, u16)
VCMP(gtuw, >, u32)
+VCMP(gtud, >, u64)
VCMP(gtsb, >, s8)
VCMP(gtsh, >, s16)
VCMP(gtsw, >, s32)
+VCMP(gtsd, >, s64)
#undef VCMP_DO
#undef VCMP
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1be5c5f..f15c21e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7134,17 +7134,27 @@ static void glue(gen_, name0##_##name1)(DisasContext
*ctx) \
GEN_VXRFORM(vcmpequb, 3, 0)
GEN_VXRFORM(vcmpequh, 3, 1)
GEN_VXRFORM(vcmpequw, 3, 2)
+GEN_VXRFORM(vcmpequd, 3, 3)
GEN_VXRFORM(vcmpgtsb, 3, 12)
GEN_VXRFORM(vcmpgtsh, 3, 13)
GEN_VXRFORM(vcmpgtsw, 3, 14)
+GEN_VXRFORM(vcmpgtsd, 3, 15)
GEN_VXRFORM(vcmpgtub, 3, 8)
GEN_VXRFORM(vcmpgtuh, 3, 9)
GEN_VXRFORM(vcmpgtuw, 3, 10)
+GEN_VXRFORM(vcmpgtud, 3, 11)
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)
GEN_VXRFORM(vcmpbfp, 3, 15)
+GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
+ vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
+ vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
+ vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
+
#define GEN_VXFORM_SIMM(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
@@ -10525,10 +10535,10 @@ GEN_VXRFORM(vcmpgtsw, 3, 14)
GEN_VXRFORM(vcmpgtub, 3, 8)
GEN_VXRFORM(vcmpgtuh, 3, 9)
GEN_VXRFORM(vcmpgtuw, 3, 10)
-GEN_VXRFORM(vcmpeqfp, 3, 3)
+GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
GEN_VXRFORM(vcmpgefp, 3, 7)
-GEN_VXRFORM(vcmpgtfp, 3, 11)
-GEN_VXRFORM(vcmpbfp, 3, 15)
+GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
+GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
#undef GEN_VXFORM_SIMM
#define GEN_VXFORM_SIMM(name, opc2, opc3) \
--
1.7.1
- [Qemu-devel] [PATCH 12/28] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes, (continued)
- [Qemu-devel] [PATCH 12/28] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 13/28] target-ppc: Altivec 2.07: Vector Population Count Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 14/28] target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 15/28] target-ppc: Altivec 2.07: Pack Doubleword Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 16/28] target-ppc: Altivec 2.07: Unpack Signed Word Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 17/28] target-ppc: Altivec 2.07: Vector Merge Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 18/28] target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 19/28] target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 20/28] target-ppc: Altivec 2.07: Quadword Addition and Subtracation, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 21/28] target-ppc: Altivec 2.07: vbpermq Instruction, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 22/28] target-ppc: Altivec 2.07: Doubleword Compares,
Tom Musta <=
- [Qemu-devel] [PATCH 23/28] target-ppc: Altivec 2.07: Vector Gather Bits by Bytes, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 24/28] target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 25/28] target-ppc: Altivec 2.07: Binary Coded Decimal Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 26/28] target-ppc: Altivec 2.07: AES Instructions, Tom Musta, 2014/02/12