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[Qemu-devel] [PATCH v2 31/35] target-arm: Implement AArch64 MPIDR
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 31/35] target-arm: Implement AArch64 MPIDR |
Date: |
Fri, 31 Jan 2014 15:45:39 +0000 |
Implement the AArch64 MPIDR system register.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a23b40d..d943963 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1435,7 +1435,8 @@ static uint64_t mpidr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
{
CPUState *cs = CPU(arm_env_get_cpu(env));
uint32_t mpidr = cs->cpu_index;
- /* We don't support setting cluster ID ([8..11])
+ /* We don't support setting cluster ID ([8..11]) (known as Aff1
+ * in later ARM ARM versions), or any of the higher affinity level fields,
* so these bits always RAZ.
*/
if (arm_feature(env, ARM_FEATURE_V7MP)) {
@@ -1450,7 +1451,8 @@ static uint64_t mpidr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
}
static const ARMCPRegInfo mpidr_cp_reginfo[] = {
- { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
+ { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
.access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
REGINFO_SENTINEL
};
--
1.8.5
- [Qemu-devel] [PATCH v2 00/35] AArch64 system mode: system register rework, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 07/35] target-arm: Add exception level to the AArch64 TB flags, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 10/35] target-arm: Stop underdecoding ARM946 PRBS registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 03/35] target-arm: Define names for SCTLR bits, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 23/35] target-arm: Implement AArch64 cache invalidate/clean ops, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 21/35] target-arm: Implement AArch64 MIDR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 25/35] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 24/35] target-arm: Implement AArch64 TLB invalidate ops, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 05/35] target-arm: Remove unused ARMCPUState sr substruct, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 14/35] target-arm: Convert miscellaneous reginfo structs to accessfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 31/35] target-arm: Implement AArch64 MPIDR,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 27/35] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 12/35] target-arm: Convert performance monitor reginfo to accesfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 33/35] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 13/35] target-arm: Convert generic timer reginfo to accessfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 16/35] target-arm: Remove unnecessary code now read/write fns can't fail, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 20/35] target-arm: Implement AArch64 CurrentEL sysreg, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 06/35] target-arm: Log bad system register accesses with LOG_UNIMP, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 29/35] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 18/35] target-arm: Fix incorrect type for value argument to write_raw_cp_reg, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/01/31