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Re: [Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise integ
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD |
Date: |
Tue, 28 Jan 2014 18:27:06 +0000 |
On 28 January 2014 17:21, Richard Henderson <address@hidden> wrote:
> On 01/26/2014 11:25 AM, Peter Maydell wrote:
>> +/* Helper functions for pairwise 32 bit comparisons */
>> +static void gen_pmax_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
>> +{
>> + tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2);
>> +}
>> +
>> +static void gen_pmax_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
>> +{
>> + tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2);
>> +}
>> +
>> +static void gen_pmin_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
>> +{
>> + tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2);
>> +}
>> +
>> +static void gen_pmin_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
>> +{
>> + tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2);
>> +}
>
> These are exactly the sort of helpers I expected to see in the previous patch.
> Thus my question re neon_{min,max}_{s,u}32.
OK, I'll move these to the previous patch and use them there too.
I suspect that the reason for teh helpers existing is they predate
the movcond op.
thanks
-- PMM
- [Qemu-devel] [PATCH 18/21] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT, (continued)
- [Qemu-devel] [PATCH 18/21] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 10/21] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 01/21] target-arm: A64: Add SIMD three-different multiply accumulate insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 21/21] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 02/21] target-arm: A64: Add SIMD three-different ABDL instructions, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 05/21] target-arm: A64: Add logic ops from SIMD 3 same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 14/21] target-arm: A64: Implement remaining integer scalar-3-same insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 03/21] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 04/21] target-arm: A64: Add top level decode for SIMD 3-same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 07/21] target-arm: A64: Add simple SIMD 3-same floating point ops, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 09/21] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns, Peter Maydell, 2014/01/26