Re: [Qemu-devel] [PATCH 3/9] target-arm: Add support for AArch32 FP VRINTR

[Peter Maydell]

On 14 January 2014 16:43, Will Newton <address@hidden> wrote:
> Add support for the AArch32 floating-point VRINTR instruction.
>
> Signed-off-by: Will Newton <address@hidden>
> ---
>  target-arm/translate.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index f688f6d..73e0e8d 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -3374,6 +3374,17 @@ static int disas_vfp_insn(CPUARMState * env, 
> DisasContext *s, uint32_t insn)
>                          gen_vfp_F1_ld0(dp);
>                          gen_vfp_cmpe(dp);
>                          break;
> +                    case 12: /* vrintr */
> +                        if (dp) {
> +                            TCGv_ptr fpst = get_fpstatus_ptr(0);
> +                            gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
> +                            tcg_temp_free_ptr(fpst);
> +                        } else {
> +                            TCGv_ptr fpst = get_fpstatus_ptr(0);
> +                            gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
> +                            tcg_temp_free_ptr(fpst);
> +                        }

Please pull the common setup/teardown of fpst out of the
two branches of this if():

    case 12: /* vrintr */
    {
         TCGv_ptr fpst = ...
         if (dp) {
                gen_helper_rintd(..)
         } else {
                gen_helper_rints(..)
         }
         tcg_temp_free...
         break;
    }

and similarly for other patches in this series (especially
where we're also doing setup/teardown of rounding mode).

thanks
-- PMM