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Re: [Qemu-devel] [PATCH v2 7/8] target-arm: A64: Add simple SIMD 3-same
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 7/8] target-arm: A64: Add simple SIMD 3-same floating point ops |
Date: |
Thu, 23 Jan 2014 17:26:51 +0000 |
On 23 January 2014 16:55, Richard Henderson <address@hidden> wrote:
> On 01/23/2014 07:28 AM, Peter Maydell wrote:
>> + /* Single */
>> + TCGv_i32 tcg_op1 = tcg_temp_new_i32();
>> + TCGv_i32 tcg_op2 = tcg_temp_new_i32();
>> + TCGv_i32 tcg_res = tcg_temp_new_i32();
>> + TCGv_i64 tcg_tmp = tcg_temp_new_i64();
>> +
>> + read_vec_element(s, tcg_tmp, rn, pass, MO_32);
>> + tcg_gen_trunc_i64_i32(tcg_op1, tcg_tmp);
>> + read_vec_element(s, tcg_tmp, rm, pass, MO_32);
>> + tcg_gen_trunc_i64_i32(tcg_op2, tcg_tmp);
>
> Update for new _i32 helpers.
Doh. Fixup patch (respin of series available on demand):
===begin===
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 5eabf24..6bc0314 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -5668,12 +5668,9 @@ static void handle_3same_float(DisasContext *s,
int size, int elements,
TCGv_i32 tcg_op1 = tcg_temp_new_i32();
TCGv_i32 tcg_op2 = tcg_temp_new_i32();
TCGv_i32 tcg_res = tcg_temp_new_i32();
- TCGv_i64 tcg_tmp = tcg_temp_new_i64();
- read_vec_element(s, tcg_tmp, rn, pass, MO_32);
- tcg_gen_trunc_i64_i32(tcg_op1, tcg_tmp);
- read_vec_element(s, tcg_tmp, rm, pass, MO_32);
- tcg_gen_trunc_i64_i32(tcg_op2, tcg_tmp);
+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
switch (fpopcode) {
case 0x1a: /* FADD */
@@ -5708,15 +5705,17 @@ static void handle_3same_float(DisasContext
*s, int size, int elements,
g_assert_not_reached();
}
- tcg_gen_extu_i32_i64(tcg_tmp, tcg_res);
if (elements == 1) {
/* scalar single so clear high part */
+ TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+
+ tcg_gen_extu_i32_i64(tcg_tmp, tcg_res);
write_vec_element(s, tcg_tmp, rd, pass, MO_64);
+ tcg_temp_free_i64(tcg_tmp);
} else {
- write_vec_element(s, tcg_tmp, rd, pass, MO_32);
+ write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
}
- tcg_temp_free_i64(tcg_tmp);
tcg_temp_free_i32(tcg_res);
tcg_temp_free_i32(tcg_op1);
tcg_temp_free_i32(tcg_op2);
===endit===
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v2 6/8] target-arm: A64: Add integer ops from SIMD 3-same group, (continued)
- [Qemu-devel] [PATCH v2 2/8] target-arm: A64: Add SIMD three-different ABDL instructions, Peter Maydell, 2014/01/23
- [Qemu-devel] [PATCH v2 5/8] target-arm: A64: Add logic ops from SIMD 3 same group, Peter Maydell, 2014/01/23
- [Qemu-devel] [PATCH v2 3/8] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops, Peter Maydell, 2014/01/23
- [Qemu-devel] [PATCH v2 8/8] target-arm: A64: Add SIMD shift by immediate, Peter Maydell, 2014/01/23
- [Qemu-devel] [PATCH v2 7/8] target-arm: A64: Add simple SIMD 3-same floating point ops, Peter Maydell, 2014/01/23