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Re: [Qemu-devel] [PATCH 8/8] target-arm: A64: Add SIMD shift by immediat
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 8/8] target-arm: A64: Add SIMD shift by immediate |
Date: |
Tue, 21 Jan 2014 13:43:18 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 |
On 01/17/2014 10:44 AM, Peter Maydell wrote:
> +/* Common SHL/SLI - Shift left with an optional insert */
> +static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
> + bool insert, int shift)
> +{
> + tcg_gen_shli_i64(tcg_src, tcg_src, shift);
> + if (insert) {
> + /* SLI */
> + uint64_t mask = (1ULL << shift) - 1;
> + tcg_gen_andi_i64(tcg_res, tcg_res, mask);
> + tcg_gen_or_i64(tcg_res, tcg_res, tcg_src);
This is
tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, shift, 64 - shift);
We do already special case such remaining-width deposits for hosts that don't
implement deposit, so we should get the exact same insn sequence for x86.
> + tcg_gen_mov_i64(tcg_res, tcg_src);
Which means for the else you can elide the move and just shift directly into
the result.
r~
Re: [Qemu-devel] [PATCH 6/8] target-arm: A64: Add integer ops from SIMD 3-same group, Richard Henderson, 2014/01/21
[Qemu-devel] [PATCH 4/8] target-arm: A64: Add top level decode for SIMD 3-same group, Peter Maydell, 2014/01/17
[Qemu-devel] [PATCH 3/8] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops, Peter Maydell, 2014/01/17