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[Qemu-devel] [PATCH 09/24] target-arm: Implement AArch64 CurrentEL sysre
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 09/24] target-arm: Implement AArch64 CurrentEL sysreg |
Date: |
Tue, 21 Jan 2014 20:12:15 +0000 |
Implement the CurrentEL sysreg.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 3 ++-
target-arm/helper.c | 3 +++
target-arm/translate-a64.c | 7 +++++++
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1dce28b..2e04a6d 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -735,7 +735,8 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
-#define ARM_LAST_SPECIAL ARM_CP_NZCV
+#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
+#define ARM_LAST_SPECIAL ARM_CP_CURRENTEL
/* Used only as a terminator for ARMCPRegInfo lists */
#define ARM_CP_SENTINEL 0xffff
/* Mask of only the flag bits in a type field */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 204d7c3..9a15b48 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1610,6 +1610,9 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
.access = PL0_R, .type = ARM_CP_CONST,
.resetvalue = 0x10 },
+ { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
+ .access = PL1_R, .type = ARM_CP_CURRENTEL },
REGINFO_SENTINEL
};
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 802d733..ae4da25 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1171,6 +1171,13 @@ static void handle_sys(DisasContext *s, uint32_t insn,
bool isread,
gen_set_nzcv(tcg_rt);
}
return;
+ case ARM_CP_CURRENTEL:
+ /* Reads as current EL value from pstate, which is
+ * guaranteed to be constant by the tb flags.
+ */
+ tcg_rt = cpu_reg(s, rt);
+ tcg_gen_movi_i64(tcg_rt, s->current_pl << 2);
+ return;
default:
break;
}
--
1.8.5
- Re: [Qemu-devel] [PATCH 18/24] target-arm: Implement AArch64 VBAR_EL1, (continued)
- [Qemu-devel] [PATCH 11/24] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 16/24] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 10/24] target-arm: Implement AArch64 MIDR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 06/24] target-arm: A64: Implement store-exclusive for system mode, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 03/24] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 12/24] target-arm: Implement AArch64 cache invalidate/clean ops, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 09/24] target-arm: Implement AArch64 CurrentEL sysreg,
Peter Maydell <=
- [Qemu-devel] [PATCH 23/24] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 22/24] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 02/24] target-arm: Define names for SCTLR bits, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 08/24] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 24/24] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 20/24] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 13/24] target-arm: Implement AArch64 TLB invalidate ops, Peter Maydell, 2014/01/21