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[Qemu-devel] [PULL 24/76] .travis.yml: Add aarch64-* targets
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 24/76] .travis.yml: Add aarch64-* targets |
Date: |
Tue, 7 Jan 2014 20:03:20 +0000 |
From: Alex Bennée <address@hidden>
Now the AArch64 targets are in mainline we can include them in our
Travis test matrix.
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
.travis.yml | 1 +
1 file changed, 1 insertion(+)
diff --git a/.travis.yml b/.travis.yml
index 90f1676..c7ff4da 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -16,6 +16,7 @@ env:
matrix:
- TARGETS=alpha-softmmu,alpha-linux-user
- TARGETS=arm-softmmu,arm-linux-user
+ - TARGETS=aarch64-softmmu,aarch64-linux-user
- TARGETS=cris-softmmu
- TARGETS=i386-softmmu,x86_64-softmmu
- TARGETS=lm32-softmmu
--
1.8.5
- [Qemu-devel] [PULL 08/76] target-arm: A64: implement SVC, BRK, (continued)
- [Qemu-devel] [PULL 08/76] target-arm: A64: implement SVC, BRK, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 74/76] target-arm: A64: Add floating-point<->integer conversion instructions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 32/76] target-arm: A64: Add support for floating point compare, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 37/76] char/cadence_uart: Add missing uart_update_state, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 14/76] target-arm: A64: Implement MRS/MSR/SYS/SYSL, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 22/76] linux-user: AArch64: define TARGET_CLONE_BACKWARDS, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 57/76] softfloat: Fix float64_to_uint64, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 30/76] target-arm: A64: Add "Floating-point data-processing (3 source)" insns, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 33/76] target-arm: A64: Add support for floating point conditional compare, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 38/76] char/cadence_uart: Fix reset., Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 24/76] .travis.yml: Add aarch64-* targets,
Peter Maydell <=
- [Qemu-devel] [PULL 27/76] target-arm: A64: Fix vector register access on bigendian hosts, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 50/76] target-arm: fix build with gcc 4.8.2, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 39/76] char/cadence_uart: s/r_fifo/rx_fifo, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 31/76] target-arm: A64: Add fmov (scalar, immediate) instruction, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 58/76] softfloat: Only raise Invalid when conversions to int are out of range, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 29/76] target-arm: A64: Add "Floating-point data-processing (2 source)" insns, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 40/76] char/cadence_uart: Simplify status generation, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 09/76] target-arm: A64: Add decoder skeleton for FP instructions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 46/76] char/cadence_uart: Implement Tx flow control, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 45/76] char/cadence_uart: Delete redundant rx rst logic, Peter Maydell, 2014/01/07