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[Qemu-devel] [RFC PATCH v4 7/8] arm_gic: Add GICC_APRn state to the GICS
From: |
Christoffer Dall |
Subject: |
[Qemu-devel] [RFC PATCH v4 7/8] arm_gic: Add GICC_APRn state to the GICState |
Date: |
Fri, 20 Dec 2013 22:09:38 -0800 |
The GICC_APRn registers are not currently supported by the ARM GIC v2.0
emulation. This patch adds the missing state.
Note that we also change the number of APRs to use a define GIC_NR_APRS
based on the maximum number of preemption levels. This patch also adds
RAZ/WI accessors for the four registers on the emulated CPU interface.
Signed-off-by: Christoffer Dall <address@hidden>
---
Changes [v3 -> v4]:
- Fixed grammatical error and use qemu_log_mask for print.
hw/intc/arm_gic.c | 5 +++++
hw/intc/arm_gic_common.c | 5 +++--
include/hw/intc/arm_gic_common.h | 11 +++++++++++
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 7ea869a..5973bdb 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -649,6 +649,8 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int
offset)
return s->current_pending[cpu];
case 0x1c: /* Aliased Binary Point */
return s->abpr[cpu];
+ case 0xd0: case 0xd4: case 0xd8: case 0xdc:
+ return s->apr[(offset - 0xd0) / 4][cpu];
default:
qemu_log_mask(LOG_GUEST_ERROR,
"gic_cpu_read: Bad offset %x\n", (int)offset);
@@ -676,6 +678,9 @@ static void gic_cpu_write(GICState *s, int cpu, int offset,
uint32_t value)
s->abpr[cpu] = (value & 0x7);
}
break;
+ case 0xd0: case 0xd4: case 0xd8: case 0xdc:
+ qemu_log_mask(LOG_UNIMP, "Writing APR not implemented\n");
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"gic_cpu_write: Bad offset %x\n", (int)offset);
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index ca12f06..f9a7a0a 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -59,8 +59,8 @@ static const VMStateDescription vmstate_gic_irq_state = {
static const VMStateDescription vmstate_gic = {
.name = "arm_gic",
- .version_id = 6,
- .minimum_version_id = 6,
+ .version_id = 7,
+ .minimum_version_id = 7,
.pre_save = gic_pre_save,
.post_load = gic_post_load,
.fields = (VMStateField[]) {
@@ -79,6 +79,7 @@ static const VMStateDescription vmstate_gic = {
VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
+ VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
VMSTATE_END_OF_LIST()
}
};
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index f37bf69..1c8bb2a 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -31,6 +31,9 @@
/* Maximum number of possible CPU interfaces, determined by GIC architecture */
#define GIC_NCPU 8
+#define MAX_NR_GROUP_PRIO 128
+#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
+
typedef struct gic_irq_state {
/* The enable bits are only banked for per-cpu interrupts. */
uint8_t enabled;
@@ -76,6 +79,14 @@ typedef struct GICState {
uint8_t bpr[GIC_NCPU];
uint8_t abpr[GIC_NCPU];
+ /* The APR is implementation defined, so we choose a layout identical to
+ * the KVM ABI layout for QEMU's implementation of the gic:
+ * If an interrupt for preemption level X is active, then
+ * APRn[X mod 32] == 0b1, where n = X / 32
+ * otherwise the bit is clear.
+ */
+ uint32_t apr[GIC_NR_APRS][GIC_NCPU];
+
uint32_t num_cpu;
MemoryRegion iomem; /* Distributor */
--
1.8.5
- [Qemu-devel] [RFC PATCH v4 0/8] Support arm-gic-kvm save/restore, Christoffer Dall, 2013/12/21
- [Qemu-devel] [RFC PATCH v4 1/8] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER, Christoffer Dall, 2013/12/21
- [Qemu-devel] [RFC PATCH v4 2/8] hw: arm_gic: Introduce gic_set_priority function, Christoffer Dall, 2013/12/21
- [Qemu-devel] [RFC PATCH v4 3/8] arm_gic: Fix GIC pending behavior, Christoffer Dall, 2013/12/21
- [Qemu-devel] [RFC PATCH v4 4/8] hw: arm_gic: Keep track of SGI sources, Christoffer Dall, 2013/12/21
- [Qemu-devel] [RFC PATCH v4 5/8] arm_gic: Support setting/getting binary point reg, Christoffer Dall, 2013/12/21
- [Qemu-devel] [RFC PATCH v4 6/8] vmstate: Add uint32 2D-array support, Christoffer Dall, 2013/12/21
- [Qemu-devel] [RFC PATCH v4 7/8] arm_gic: Add GICC_APRn state to the GICState,
Christoffer Dall <=
- [Qemu-devel] [RFC PATCH v4 8/8] hw: arm_gic_kvm: Add KVM VGIC save/restore logic, Christoffer Dall, 2013/12/21