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[Qemu-devel] [PULL 28/62] target-arm: A64: provide functions for accessi
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 28/62] target-arm: A64: provide functions for accessing FPCR and FPSR |
Date: |
Tue, 17 Dec 2013 20:28:46 +0000 |
The information which AArch32 holds in the FPSCR is split for
AArch64 into two logically distinct registers, FPSR and FPCR.
Since they are carefully arranged to use non-overlapping bits,
we leave the underlying state in the same place, and provide
accessor functions which just update the appropriate bits
via vfp_get_fpscr() and vfp_set_fpscr().
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/cpu.h | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3af4ed3..56ed591 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -447,6 +447,34 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
uint32_t vfp_get_fpscr(CPUARMState *env);
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
+/* For A64 the FPSCR is split into two logically distinct registers,
+ * FPCR and FPSR. However since they still use non-overlapping bits
+ * we store the underlying state in fpscr and just mask on read/write.
+ */
+#define FPSR_MASK 0xf800009f
+#define FPCR_MASK 0x07f79f00
+static inline uint32_t vfp_get_fpsr(CPUARMState *env)
+{
+ return vfp_get_fpscr(env) & FPSR_MASK;
+}
+
+static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
+{
+ uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
+ vfp_set_fpscr(env, new_fpscr);
+}
+
+static inline uint32_t vfp_get_fpcr(CPUARMState *env)
+{
+ return vfp_get_fpscr(env) & FPCR_MASK;
+}
+
+static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
+{
+ uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
+ vfp_set_fpscr(env, new_fpscr);
+}
+
enum arm_cpu_mode {
ARM_CPU_MODE_USR = 0x10,
ARM_CPU_MODE_FIQ = 0x11,
--
1.8.5
- [Qemu-devel] [PULL 17/62] ARM: cpu: add "reset_hivecs" property, (continued)
- [Qemu-devel] [PULL 17/62] ARM: cpu: add "reset_hivecs" property, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 09/62] target-arm/helper.c: Allow cp15.c15 dummy override, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 06/62] Add max device width parameter for NOR devices, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 01/62] target-arm: add support for v8 AES instructions, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 19/62] target-arm/kvm: Split 32 bit only code into its own file, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 57/62] vmstate: Add support for an array of ptimer_state *, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 34/62] target-arm: A64: add support for BR, BLR and RET insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 35/62] target-arm: A64: add support for conditional branches, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 16/62] arm/highbank.c: Fix MPCore periphbase name, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 32/62] target-arm: A64: expand decoding skeleton for system instructions, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 28/62] target-arm: A64: provide functions for accessing FPCR and FPSR,
Peter Maydell <=
- [Qemu-devel] [PULL 25/62] default-configs: Add config for aarch64-softmmu, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 27/62] target-arm: A64: add set_pc cpu method, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 33/62] target-arm: A64: add support for B and BL insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 31/62] target-arm: A64: provide skeleton for a64 insn decoding, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 30/62] target-arm: A64: add stubs for a64 specific helpers, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 29/62] target-arm: Support fp registers in gdb stub, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 15/62] arm/xilinx_zynq: Implement CBAR initialisation, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 61/62] hw/arm: add cubieboard support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 36/62] target-arm: A64: add support for 'test and branch' imm, Peter Maydell, 2013/12/17
- Re: [Qemu-devel] [PULL 00/62] target-arm queue, Anthony Liguori, 2013/12/19