Re: [Qemu-devel] [PATCH 2/7] target-arm: Clean up handling of AArch64 PSTATE

[Peter Maydell]

On 17 December 2013 04:45, Christoffer Dall <address@hidden> wrote:
> I think this could be written slightly more clearly for the uninitiated,
> but maybe I'm just not qemu-savy enough.

It was a bit compressed; I've reworded it to:
    /* PSTATE isn't an architectural register for ARMv8. However, it is
     * convenient for us to assemble the underlying state into a 32 bit format
     * identical to the architectural format used for the SPSR. (This is also
     * what the Linux kernel's 'pstate' field in signal handlers and KVM's
     * 'pstate' register are.) Of the PSTATE bits:
     *  NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
     *    semantics as for AArch32, as described in the comments on each field)
     *  nRW (also known as M[4]) is kept, inverted, in env->aarch64
     *  all other bits are stored in their correct places in env->pstate
     */

thanks
-- PMM