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Re: [Qemu-devel] [PATCH v3 7/8] target-arm: A64: add support for 3 src d
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v3 7/8] target-arm: A64: add support for 3 src data proc insns |
Date: |
Mon, 16 Dec 2013 09:36:56 +0000 |
On 16 December 2013 08:54, Claudio Fontana <address@hidden> wrote:
> Hello Peter,
>
> On 13.12.2013 20:18, Peter Maydell wrote:
>> From: Alexander Graf <address@hidden>
>>
>> This patch adds emulation for the "Data-processing (3 source)"
>> family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH,
>> UMADDL, UMSUBL, UMULH.
>>
>> Signed-off-by: Alexander Graf <address@hidden>
>> Signed-off-by: Alex Bennée <address@hidden>
>> Signed-off-by: Peter Maydell <address@hidden>
>> ---
>> target-arm/translate-a64.c | 91
>> +++++++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 89 insertions(+), 2 deletions(-)
>>
>> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
>> index a6f1945..b3e9449 100644
>> --- a/target-arm/translate-a64.c
>> +++ b/target-arm/translate-a64.c
>> @@ -2125,10 +2125,97 @@ static void disas_add_sub_reg(DisasContext *s,
>> uint32_t insn)
>> tcg_temp_free_i64(tcg_result);
>> }
>>
>> -/* Data-processing (3 source) */
>> +/* C3.5.9 Data-processing (3 source)
>> +
>> + 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
>> + +--+------+-----------+------+------+----+------+------+------+
>> + |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
>> + +--+------+-----------+------+------+----+------+------+------+
>> +
>> + */
>> static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
>> {
>> - unsupported_encoding(s, insn);
>> + int rd = extract32(insn, 0, 5);
>> + int rn = extract32(insn, 5, 5);
>> + int ra = extract32(insn, 10, 5);
>> + int rm = extract32(insn, 16, 5);
>> + int op_id = (extract32(insn, 29, 3) << 4) |
>> + (extract32(insn, 21, 3) << 1) |
>> + extract32(insn, 15, 1);
>> + bool is_32bit = !extract32(insn, 31, 1);
>
> we have used "sf" everywhere else..
Yes, might as well be consistent.
>> + tcg_temp_free(low_bits);
>
> should this be tcg_temp_free_i64()?
Yes, since we're preferring to be explicit about i32 vs i64
temps. (We know we're always building a 64 bit binary for
translate-a64.c so in fact we can guarantee that tcg_temp_free
is always tcg_temp_free_i64; but consistency with the 32 bit
decoder is nice.)
Fixed these nits in my working tree.
thanks
-- PMM
- [Qemu-devel] [PATCH v3 0/8] target-arm: A64 decoder set 3: loads, stores, misc integer, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 7/8] target-arm: A64: add support for 3 src data proc insns, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 2/8] target-arm: A64: add support for ld/st unsigned imm, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 8/8] target-arm: A64: implement SVC, BRK, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 1/8] target-arm: A64: add support for ld/st pair, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 6/8] target-arm: A64: add support for move wide instructions, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 5/8] target-arm: A64: add support for add, addi, sub, subi, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 4/8] target-arm: A64: add support for ld/st with index, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 3/8] target-arm: A64: add support for ld/st with reg offset, Peter Maydell, 2013/12/13