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Re: [Qemu-devel] [PATCH v2 02/13] target-arm: A64: add support for logic
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v2 02/13] target-arm: A64: add support for logical (shifted register) |
Date: |
Sat, 07 Dec 2013 06:02:46 +1300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 |
On 12/07/2013 02:19 AM, Peter Maydell wrote:
> From: Alexander Graf <address@hidden>
>
> Add support for the instructions described in "C3.5.10 Logical
> (shifted register)".
>
> We store the flags in the same locations as the 32 bit decoder.
> This is slightly awkward when calculating 64 bit results, but seems
> a better tradeoff than having to rework the whole 32 bit decoder
> and also make 32 bit result calculation in A64 awkward.
>
> Signed-off-by: Alexander Graf <address@hidden>
> [claudio: some refactoring to avoid hidden allocation of temps,
> rework flags, use enums for shift types,
> renaming of functions]
> Signed-off-by: Claudio Fontana <address@hidden>
> [PMM: Use TCG's andc/orc/eqv ops rather than manually inverting]
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target-arm/translate-a64.c | 197
> ++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 191 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-devel] [PATCH v2 00/13] target-arm: A64 decoder set 2: misc logic and bit ops, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 02/13] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/06
- Re: [Qemu-devel] [PATCH v2 02/13] target-arm: A64: add support for logical (shifted register),
Richard Henderson <=
- [Qemu-devel] [PATCH v2 06/13] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 08/13] target-arm: A64: add support for 1-src RBIT insn, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 01/13] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 04/13] target-arm: A64: add support for EXTR, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 05/13] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 09/13] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 13/13] target-arm: A64: add support for logical (immediate) insns, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/06