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[Qemu-devel] [RFC PATCH 13/21] target-arm: add SDER definition
From: |
Sergey Fedorov |
Subject: |
[Qemu-devel] [RFC PATCH 13/21] target-arm: add SDER definition |
Date: |
Tue, 03 Dec 2013 12:48:47 +0400 |
Signed-off-by: Sergey Fedorov <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5aeb630..ffc1b21 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -150,6 +150,7 @@ typedef struct CPUARMState {
uint32_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint32_t c1_scr; /* secure config register. */
+ uint32_t c1_sder; /* Secure debug enable register. */
uint32_t c1_nsacr; /* Non-secure access control register. */
uint32_t c2_base0; /* MMU translation table base 0. */
uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b6d8a3c..780d0a0 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1560,6 +1560,9 @@ static const ARMCPRegInfo tz_cp_reginfo[] = {
.access = PL1_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
.resetvalue = 0 },
+ { .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1,
+ .access = PL3_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c1_sder) },
{ .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2,
.access = PL3_RW | PL2_R, .resetvalue = 0, .writefn = nsacr_write,
.fieldoffset = offsetof(CPUARMState, cp15.c1_nsacr) },
--
1.7.9.5
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, (continued)
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Peter Crosthwaite, 2013/12/21
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Peter Maydell, 2013/12/22
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Fedorov Sergey, 2013/12/23
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Fedorov Sergey, 2013/12/23
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Peter Maydell, 2013/12/23
[Qemu-devel] [RFC PATCH 15/21] target-arm: add banked coprocessor register type, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 16/21] target-arm: convert appropriate coprocessor registers to banked type, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 13/21] target-arm: add SDER definition,
Sergey Fedorov <=
[Qemu-devel] [RFC PATCH 02/21] target-arm: move SCR & VBAR into TrustZone register list, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 06/21] target-arm: add arm_is_secure() helper, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 20/21] target-arm: implement SMC instruction, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 19/21] target-arm: add MVBAR support, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 21/21] target-arm: implement IRQ/FIQ routing to Monitor mode, Sergey Fedorov, 2013/12/03
Re: [Qemu-devel] [RFC PATCH 00/21] target-arm: add CPU core TrustZone support, Fedorov Sergey, 2013/12/04