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Re: [Qemu-devel] [PATCH 03/13] target-openrisc: Separate of load/store i
From: |
Max Filippov |
Subject: |
Re: [Qemu-devel] [PATCH 03/13] target-openrisc: Separate of load/store instructions |
Date: |
Wed, 30 Oct 2013 02:55:06 +0400 |
On Wed, Oct 30, 2013 at 1:36 AM, Sebastian Macke <address@hidden> wrote:
> On 29/10/2013 1:05 PM, Max Filippov wrote:
>>
>> On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke <address@hidden>
>> wrote:
>>> Additional this patch solves a severe bug for the softmmu emulation.
>>> The pc has to be saved as these instructions can fail and lead
>>> to a tlb miss exception.
>>
>> In case of an exception we re-translate the TB to find the PC where
>> the exception happened, see cpu_restore_state call from the tlb_fill
>> function. Also this applies to both user and system emulation, but
>> you only handle the system emulation case.
>
> The problem is the epcr register in the interrupt routine in which the
> current pc must be saved.
> Of course in the user emulation case the interrupt handler is never
> executed.
>
> When is the pc of the fault determined? Before or after the interrupt
> handler?
Before, in the tlb_fill: cpu_restore_state is called to restore context,
and after that cpu_loop_exit is called to handle the exception.
> Finding this problem gave me a long headache. But it would be nice if there
> is a better solution.
--
Thanks.
-- Max
- [Qemu-devel] [PATCH 01/13] target-openrisc: Implement translation block chaining, (continued)
[Qemu-devel] [PATCH 03/13] target-openrisc: Separate of load/store instructions, Sebastian Macke, 2013/10/29
[Qemu-devel] [PATCH 04/13] target-openrisc: sync flags only when necessary, Sebastian Macke, 2013/10/29
[Qemu-devel] [PATCH 02/13] target-openrisc: Separate Delayed slot handling from main loop, Sebastian Macke, 2013/10/29
[Qemu-devel] [PATCH 07/13] target-openrisc: Correct l.cmov conditional check, Sebastian Macke, 2013/10/29
[Qemu-devel] [PATCH 05/13] target-openrisc: Remove TLB flush on exception, Sebastian Macke, 2013/10/29