Re: [Qemu-devel] [PATCH 09/60] AArch64: Add b and bl handling

[Richard Henderson]

On 09/26/2013 05:48 PM, Alexander Graf wrote:
> +static int get_bits(uint32_t inst, int start, int len)
> +{
> +    return (inst >> start) & ((1 << len) - 1);
> +}
> +
> +static int get_sbits(uint32_t inst, int start, int len)
> +{
> +    int r = get_bits(inst, start, len);
> +    if (r & (1 << (len - 1))) {
> +        /* Extend the MSB 1 to the higher bits */
> +        r |= -1 & ~((1ULL << len) - 1);
> +    }
> +    return r;
> +}

extract32 and sextract32 please.

> +static TCGv_i64 cpu_reg(int reg)
> +{
> +    if (reg == 31) {
> +        /* XXX leaks temps */
> +        return tcg_const_i64(0);
> +    } else {
> +        return cpu_X[reg];
> +    }
> +}

See how we treat temporaries in the sparc translator.
We record them in the DisasContext to be freed at the
end of the insn.

> +    tb = s->tb;
> +    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {

Not the only conditions you need to check.  In
particular, no single-stepping or tb->flags & CF_LAST_IO.
C.f. target-alpha's use_goto_tb function.


r~