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[Qemu-devel] [PATCH 54/60] AArch64: Add "Floating-point data-processing
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 54/60] AArch64: Add "Floating-point data-processing (1 |
Date: |
Fri, 27 Sep 2013 02:48:48 +0200 |
This patch adds emulation for the "Floating-point data-processing (1 source)"
group of instructions in their 32 bit flavors.
Signed-off-by: Alexander Graf <address@hidden>
---
target-arm/helper-a64.c | 5 +++
target-arm/helper-a64.h | 1 +
target-arm/translate-a64.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 85 insertions(+)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 0b7aee1..b430823 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -297,3 +297,8 @@ void HELPER(set_rmode)(uint32_t rmode, void *fp_status)
set_float_rounding_mode(rmode, fp_status);
}
+
+float32 HELPER(rints)(float32 x, void *fp_status)
+{
+ return float32_round_to_int(x, fp_status);
+}
diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h
index f42edf8..4dbc56a 100644
--- a/target-arm/helper-a64.h
+++ b/target-arm/helper-a64.h
@@ -31,3 +31,4 @@ DEF_HELPER_FLAGS_1(clz64, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_2(umulh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(smulh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_2(set_rmode, void, i32, ptr)
+DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG_SE, f32, f32, ptr)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 948e5c4..52ecef4 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2038,6 +2038,82 @@ static void handle_fcmp(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tcg_op2_32);
}
+/* Floating-point data-processing (1 source) - 32 bit */
+static void handle_fpdp1s32(DisasContext *s, uint32_t insn)
+{
+ int rd = get_bits(insn, 0, 5);
+ int rn = get_bits(insn, 5, 5);
+ int opcode = get_bits(insn, 15, 6);
+ int freg_offs_n = offsetof(CPUARMState, vfp.regs[rn * 2]);
+ int freg_offs_d = offsetof(CPUARMState, vfp.regs[rd * 2]);
+ TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+ TCGv_i32 tcg_op = tcg_temp_new_i32();
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
+ TCGv_ptr fpst = get_fpstatus_ptr();
+ bool skip_write = false;
+
+ tcg_gen_ld_i64(tcg_tmp, cpu_env, freg_offs_n);
+ tcg_gen_trunc_i64_i32(tcg_op, tcg_tmp);
+
+ switch (opcode) {
+ case 0x0: /* FMOV */
+ tcg_gen_mov_i32(tcg_res, tcg_op);
+ break;
+ case 0x1: /* FABS */
+ gen_helper_vfp_abss(tcg_res, tcg_op);
+ break;
+ case 0x2: /* FNEG */
+ gen_helper_vfp_negs(tcg_res, tcg_op);
+ break;
+ case 0x3: /* FSQRT */
+ gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
+ break;
+ case 0x5: /* FCVT (single to double) */
+ skip_write = true;
+ gen_helper_vfp_fcvtds(tcg_tmp, tcg_op, cpu_env);
+ clear_fpreg(rd);
+ tcg_gen_st_i64(tcg_tmp, cpu_env, freg_offs_d);
+ break;
+ case 0x7: /* FCVT (single to half) */
+ /* XXX */
+ unallocated_encoding(s);
+ return;
+ case 0x8: /* FRINTN XXX add rounding mode */
+ case 0x9: /* FRINTP */
+ case 0xa: /* FRINTM */
+ case 0xb: /* FRINTZ */
+ case 0xc: /* FRINTA */
+ case 0xe: /* FRINTX */
+ case 0xf: /* FRINTI */
+ {
+ TCGv_i32 tcg_rmode = tcg_const_i32(opcode & 7);
+
+ gen_helper_set_rmode(tcg_rmode, fpst);
+ gen_helper_rints(tcg_res, tcg_op, fpst);
+
+ /* XXX use fpcr */
+ tcg_gen_movi_i32(tcg_rmode, -1);
+ gen_helper_set_rmode(tcg_rmode, fpst);
+ tcg_temp_free_i32(tcg_rmode);
+ break;
+ }
+ default:
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (!skip_write) {
+ clear_fpreg(rd);
+ tcg_gen_ext32u_i64(tcg_tmp, tcg_res);
+ tcg_gen_st32_i64(tcg_tmp, cpu_env, freg_offs_d);
+ }
+
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(tcg_op);
+ tcg_temp_free_i32(tcg_res);
+ tcg_temp_free_i64(tcg_tmp);
+}
+
/* SIMD ORR */
static void handle_simdorr(DisasContext *s, uint32_t insn)
{
@@ -2629,6 +2705,9 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
} else if (!get_bits(insn, 29, 3) && get_bits(insn, 21, 1) &&
(get_bits(insn, 10, 6) == 0x8) && !get_bits(insn, 0, 3)) {
handle_fcmp(s, insn);
+ } else if (!get_bits(insn, 29, 3) && !get_bits(insn, 22, 2) &&
+ get_bits(insn, 21, 1) && (get_bits(insn, 10, 5) == 0x10)) {
+ handle_fpdp1s32(s, insn);
} else {
unallocated_encoding(s);
}
--
1.7.12.4
- [Qemu-devel] [PATCH 49/60] AArch64: Add "Data-processing (3 source)" instruction, (continued)
- [Qemu-devel] [PATCH 49/60] AArch64: Add "Data-processing (3 source)" instruction, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 51/60] AArch64: Add fmov (scalar, immediate) instruction, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 56/60] AArch64: Add "Floating-point data-processing (2, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 58/60] AArch64: Add "ADD (vector)" instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 57/60] AArch64: Add "Floating-point data-processing (2, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 42/60] AArch64: Add literal ld instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 50/60] AArch64: Add "Floating-point<->fixed-point, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 52/60] AArch64: Add "Floating-point<->integer conversions", Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 59/60] AArch64: Add "Floating-point data-processing (3, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 53/60] AArch64: Add "Floating-point compare" instruction, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 54/60] AArch64: Add "Floating-point data-processing (1,
Alexander Graf <=
- [Qemu-devel] [PATCH 60/60] AArch64: Add "Floating-point data-processing (3, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 55/60] AArch64: Add "Floating-point data-processing (1, Alexander Graf, 2013/09/26
- Re: [Qemu-devel] [PATCH 00/60] AArch64 TCG emulation support, Alexander Graf, 2013/09/26