Re: [Qemu-devel] [PATCH] hw/pci: completed master-abort emulation

[Marcel Apfelbaum]

On Tue, 2013-09-24 at 11:58 +0300, Michael S. Tsirkin wrote:
> corrected Anthony's mail.
> 
> On Tue, Sep 24, 2013 at 11:44:57AM +0300, Marcel Apfelbaum wrote:
> > > Not necessarily. Another bridge can claim it then
> > > terminate with MA.
> > > 
> > > Example:
> > > 
> > > -[0000:00]-+-00.0
> > >            +-02.0
> > >            +-16.0
> > >            +-16.3
> > >            +-19.0
> > >            +-1a.0
> > >            +-1b.0
> > >            +-1c.0-[02]--
> > >            +-1c.1-[03]----00.0
> > >            +-1c.3-[05-0c]--
> > >            +-1c.4-[0d]--+-00.0
> > >            |            \-00.3
> > > 
> > > 
> > > 
> > > Device 03:00.0 writes to within memory window of 00:1c.4,
> > > but outside BARs of both 0d:00.0 and 0d:00.3.
> > > 
> > > On PCI, I think MA is set in sec status register of 00:1c.4.
> > You are right, my code will work only under the assumption
> > that the devices do not communicate between them.
> > I will state the above in the next version.
> > 
> > Thanks,
> > Marcel
> 
> How hard is it to fix properly?
We need to check all the bridges on each bus encountered 
for their address range; if it corresponds to the transaction address,
we pass the bridge to the other bus(depending on transaction's direction).

> If that's hard, would it be easier to implement express
> semantics unconditionally?
I think PCI Express would follow the same algorithm anyway,
Thanks,
Marcel

> 
>