Re: [Qemu-devel] [PATCH RFC v2 2/2] hw/pci: handle unassigned pci addresses

[Michael S. Tsirkin]

On Sun, Sep 15, 2013 at 03:49:00PM +0100, Peter Maydell wrote:
> On 15 September 2013 15:20, Michael S. Tsirkin <address@hidden> wrote:
> > On Sun, Sep 15, 2013 at 03:08:38PM +0100, Peter Maydell wrote:
> >> Well, that's your choice, but I'd be really surprised if the
> >> PCI controller allowed PCI BARs to get mapped over the
> >> top of builtin devices like that.
> >
> > Well it has no way not to allow this
> 
> The key phrase there was "over the top". The controller and/or
> the bus fabric can choose to direct accesses to these addresses
> to the builtin device regardless of what the PCI BARs are mapped
> as. It's that choice that we're modelling when we set the priorities of
> overlapping regions.
> 
> >> It's still an odd corner case that only the PCI controller
> >> core code needs to care about
> >
> > Actually you previosly wrote:
> >         > the versatilePB's PCI controller only responds to accesses
> >         > within its programmed MMIO BAR ranges, so if the device
> >         > or the controller have been misconfigured you can get an
> >         > abort when the device tries to do DMA.
> > Doesn't this mean versatilePB will have to have
> > similar code in it's PCI controller implementation -
> > outside PCI controller core?
> 
> If you implement PCI bus mastering sufficiently accurately in the
> PCI core code, then maybe not

Well it's not about implementation I think:
RAM is not on the PCI bus, is it?
If it's not on the PCI bus I doubt RAM accesses
can cause master aborts on the PCI bus: PCI host
would have to claim and then possibly discard them.

> (DMA to the system RAM on
> a versatilePB really does look exactly like any PCI device doing
> a bus master access to any other); we'll see.
> 
> -- PMM

Well PCI device access to another PCI device looks
differently depending on whether the other device
is on the same bus, or not.

When it's on the same bus, device detects master abort.
When it's on a different bus (across a bridge),
bridge detects master abort, device detects completion.

-- 
MST