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Re: [Qemu-devel] [PATCH] target-mips: fix decoding of microMIPS POOL32Ax
From: |
Maciej W. Rozycki |
Subject: |
Re: [Qemu-devel] [PATCH] target-mips: fix decoding of microMIPS POOL32Axf instructions |
Date: |
Fri, 13 Sep 2013 17:42:36 +0100 |
User-agent: |
Alpine 1.10 (DEB 962 2008-03-14) |
On Mon, 5 Aug 2013, Leon Alrae wrote:
> Just to make sure that we are refering to the same thing :)
> For MFHI:
> page no. 303 in MIPS Architecture for Programmers Volume II-B: The
> microMIPS32 Instruction Set (document MD00764)
> page no. 140 in MIPS Architecture for Programmers Volume IV-e: The MIPS
> DSP Module for the microMIPS32 Architecture (document MD00582)
Where instruction encoding is concerned please remember to always refer
to opcode tables rather than individual instruction description pages in
case there is a documentation erratum. If that happens, then opcode
tables take precedence as they are generated automatically from actual
architecture descriptions. We had such a case already actually that was
spotted late enough that it was architecture that had to be modified to
match software expectations (QEMU included).
So in this case it is:
Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field, p. 498,
"MIPS Architecture for Programmers, Volume II-B: The microMIPS32
Instruction Set", Document Number: MD00582, Revision 5.01, December 16,
2012
and:
Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field, p. 66, "MIPS
Architecture for Programmers, VolumeIV-e: The MIPSR DSP Module for the
microMIPS32 Architecture", Document Number: MD00764, Revision 2.40,
December 16, 2012
that you should be referring to (note that you've got the document numbers
reversed too ;) ).
I agree it looks weird and wasteful to have two separate encodings for
instructions that operate on the HI[0] and LO[0] registers, but I suppose
it makes the wiring of the DSP Disabled exception easier.
Maciej
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Maciej W. Rozycki <=