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[Qemu-devel] [PULL 03/28] target-arm: Avoid "1 << 31" undefined behaviou
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/28] target-arm: Avoid "1 << 31" undefined behaviour |
Date: |
Tue, 10 Sep 2013 19:51:57 +0100 |
Avoid the undefined behaviour of "1 << 31" by using 1U to make
the shift be of an unsigned value rather than shifting into the
sign bit of a signed integer. For consistency, we make all the
CPSR_* constants unsigned, though the only one which triggers
undefined behaviour is CPSR_N.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target-arm/cpu.h | 32 ++++++++++++++++----------------
target-arm/helper.c | 4 ++--
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f2abdf3..af7cf8a 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -270,22 +270,22 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env,
target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
-#define CPSR_M (0x1f)
-#define CPSR_T (1 << 5)
-#define CPSR_F (1 << 6)
-#define CPSR_I (1 << 7)
-#define CPSR_A (1 << 8)
-#define CPSR_E (1 << 9)
-#define CPSR_IT_2_7 (0xfc00)
-#define CPSR_GE (0xf << 16)
-#define CPSR_RESERVED (0xf << 20)
-#define CPSR_J (1 << 24)
-#define CPSR_IT_0_1 (3 << 25)
-#define CPSR_Q (1 << 27)
-#define CPSR_V (1 << 28)
-#define CPSR_C (1 << 29)
-#define CPSR_Z (1 << 30)
-#define CPSR_N (1 << 31)
+#define CPSR_M (0x1fU)
+#define CPSR_T (1U << 5)
+#define CPSR_F (1U << 6)
+#define CPSR_I (1U << 7)
+#define CPSR_A (1U << 8)
+#define CPSR_E (1U << 9)
+#define CPSR_IT_2_7 (0xfc00U)
+#define CPSR_GE (0xfU << 16)
+#define CPSR_RESERVED (0xfU << 20)
+#define CPSR_J (1U << 24)
+#define CPSR_IT_0_1 (3U << 25)
+#define CPSR_Q (1U << 27)
+#define CPSR_V (1U << 28)
+#define CPSR_C (1U << 29)
+#define CPSR_Z (1U << 30)
+#define CPSR_N (1U << 31)
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e51ef20..c1a68c7 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -972,7 +972,7 @@ static int par_write(CPUARMState *env, const ARMCPRegInfo
*ri, uint64_t value)
static inline bool extended_addresses_enabled(CPUARMState *env)
{
return arm_feature(env, ARM_FEATURE_LPAE)
- && (env->cp15.c2_control & (1 << 31));
+ && (env->cp15.c2_control & (1U << 31));
}
static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
@@ -1385,7 +1385,7 @@ static int mpidr_read(CPUARMState *env, const
ARMCPRegInfo *ri,
* so these bits always RAZ.
*/
if (arm_feature(env, ARM_FEATURE_V7MP)) {
- mpidr |= (1 << 31);
+ mpidr |= (1U << 31);
/* Cores which are uniprocessor (non-coherent)
* but still implement the MP extensions set
* bit 30. (For instance, A9UP.) However we do
--
1.7.9.5
- [Qemu-devel] [PULL 19/28] linux-user: Add cpu loop for AArch64, (continued)
- [Qemu-devel] [PULL 19/28] linux-user: Add cpu loop for AArch64, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 18/28] linux-user: Don't treat AArch64 cpu names specially, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 24/28] linux-user: Implement cpu_set_tls() and cpu_clone_regs() for AArch64, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 10/28] target-arm: Export cpu_env, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 20/28] linux-user: Add syscall number definitions for AArch64, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 07/28] abitypes.h: Remove incorrect ARM ABI_LLONG_ALIGNMENT, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 14/28] target-arm: Disable 32 bit CPUs in 64 bit linux-user builds, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 27/28] linux-user: Add AArch64 support, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 22/28] linux-user: Add signal handling for AArch64, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 16/28] target-arm: Add AArch64 translation stub, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 03/28] target-arm: Avoid "1 << 31" undefined behaviour,
Peter Maydell <=
- [Qemu-devel] [PULL 01/28] target-arm: Make '-cpu any' available in linux-user mode only, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 13/28] target-arm: Add new AArch64CPUInfo base class and subclasses, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 09/28] target-arm: Extract the disas struct to a header file, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 11/28] target-arm: Fix target_ulong/uint32_t confusions, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 02/28] target-arm: Use sextract32() in branch decode, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 12/28] target-arm: Pass DisasContext* to gen_set_pc_im(), Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 17/28] target-arm: Add AArch64 gdbstub support, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 05/28] target-arm: Implement qmp query-cpu-definitions, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 04/28] target-arm: fix ARMv7M stack alignment on reset, Peter Maydell, 2013/09/10
- [Qemu-devel] [PULL 08/28] target-arm: Abstract out load/store from a vaddr in AArch32, Peter Maydell, 2013/09/10