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[Qemu-devel] [PATCH 11/19] tcg-ia64 Introduce tcg_opc_movi_a
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 11/19] tcg-ia64 Introduce tcg_opc_movi_a |
Date: |
Thu, 5 Sep 2013 23:50:33 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ia64/tcg-target.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 3e96af9..8057f40 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -879,6 +879,12 @@ static inline void tcg_out_mov(TCGContext *s, TCGType type,
tcg_opc_mov_a(TCG_REG_P0, ret, arg));
}
+static inline uint64_t tcg_opc_movi_a(int qp, TCGReg dst, int64_t src)
+{
+ assert(src == sextract64(src, 0, 22));
+ return tcg_opc_a5(qp, OPC_ADDL_A5, dst, src, TCG_REG_R0);
+}
+
static inline void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg reg, tcg_target_long arg)
{
@@ -1056,16 +1062,14 @@ static inline void tcg_out_alu(TCGContext *s, uint64_t
opc_a1, uint64_t opc_a3,
uint64_t opc1 = 0, opc2 = 0, opc3 = 0;
if (const_arg2 && arg2 != 0) {
- opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
- TCG_REG_R3, arg2, TCG_REG_R0);
+ opc2 = tcg_opc_movi_a(TCG_REG_P0, TCG_REG_R3, arg2);
arg2 = TCG_REG_R3;
}
if (const_arg1 && arg1 != 0) {
if (opc_a3 && arg1 == (int8_t)arg1) {
opc3 = tcg_opc_a3(TCG_REG_P0, opc_a3, ret, arg1, arg2);
} else {
- opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
- TCG_REG_R2, arg1, TCG_REG_R0);
+ opc1 = tcg_opc_movi_a(TCG_REG_P0, TCG_REG_R2, arg1);
arg1 = TCG_REG_R2;
}
}
@@ -1429,8 +1433,7 @@ static inline void tcg_out_deposit(TCGContext *s, TCGArg
ret, TCGArg a1,
} else {
/* Otherwise, load any constant into a temporary. Do this into
the first I slot to help out with cross-unit delays. */
- i1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
- TCG_REG_R2, a2, TCG_REG_R0);
+ i1 = tcg_opc_movi_a(TCG_REG_P0, TCG_REG_R2, a2);
a2 = TCG_REG_R2;
}
}
@@ -1509,8 +1512,8 @@ static inline void tcg_out_setcond(TCGContext *s, TCGCond
cond, TCGArg ret,
{
tcg_out_bundle(s, MmI,
tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
- tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
- tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
+ tcg_opc_movi_a(TCG_REG_P6, ret, 1),
+ tcg_opc_movi_a(TCG_REG_P7, ret, 0));
}
static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
@@ -1521,14 +1524,14 @@ static inline void tcg_out_movcond(TCGContext *s,
TCGCond cond, TCGArg ret,
uint64_t opc1, opc2;
if (const_v1) {
- opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0);
+ opc1 = tcg_opc_movi_a(TCG_REG_P6, ret, v1);
} else if (ret == v1) {
opc1 = INSN_NOP_M;
} else {
opc1 = tcg_opc_mov_a(TCG_REG_P6, ret, v1);
}
if (const_v2) {
- opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0);
+ opc2 = tcg_opc_movi_a(TCG_REG_P7, ret, v2);
} else if (ret == v2) {
opc2 = INSN_NOP_I;
} else {
@@ -1647,15 +1650,13 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const
TCGArg *args,
}
if (!bswap) {
tcg_out_bundle(s, miB,
- tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
- mem_index, TCG_REG_R0),
+ tcg_opc_movi_a(TCG_REG_P7, TCG_REG_R58, mem_index),
INSN_NOP_I,
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
TCG_REG_B0, TCG_REG_B6));
} else {
tcg_out_bundle(s, miB,
- tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
- mem_index, TCG_REG_R0),
+ tcg_opc_movi_a(TCG_REG_P7, TCG_REG_R58, mem_index),
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
TCG_REG_R8, TCG_REG_R8, 0xb),
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
@@ -1776,8 +1777,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const
TCGArg *args,
tcg_out_bundle(s, miB,
tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
data_reg, TCG_REG_R3),
- tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
- mem_index, TCG_REG_R0),
+ tcg_opc_movi_a(TCG_REG_P7, TCG_REG_R59, mem_index),
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
TCG_REG_B0, TCG_REG_B6));
}
--
1.8.3.1
- [Qemu-devel] [PATCH 01/19] tcg-ia64: Use TCGMemOp within qemu_ldst routines, (continued)
- [Qemu-devel] [PATCH 01/19] tcg-ia64: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 02/19] tcg-ia64: Use shortcuts for nop insns, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 04/19] tcg-ia64: Simplify brcond, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 03/19] tcg-ia64: Handle constant calls, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 05/19] tcg-ia64: Move AREG0 to R32, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 06/19] tcg-ia64: Avoid unnecessary stop bit in tcg_out_alu, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 08/19] tcg-ia64: Use SUB_A3 and ADDS_A4 for subtraction, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 07/19] tcg-ia64: Use ADDS for small addition, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 09/19] tcg-ia64: Use A3 form of logical operations, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 10/19] tcg-ia64 Introduce tcg_opc_mov_a, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 11/19] tcg-ia64 Introduce tcg_opc_movi_a,
Richard Henderson <=
- [Qemu-devel] [PATCH 12/19] tcg-ia64 Introduce tcg_opc_ext_i, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 13/19] tcg-ia64 Introduce tcg_opc_bswap64_i, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 14/19] tcg-ia64: Re-bundle the tlb load, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 15/19] tcg-ia64: Move bswap for store into tlb load, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 16/19] tcg-ia64: Move tlb addend load into tlb read, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 17/19] tcg-i64: Reduce code duplication in tcg_out_qemu_ld, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 18/19] tcg-ia64: Convert to new ldst helpers, Richard Henderson, 2013/09/06
- [Qemu-devel] [PATCH 19/19] tcg-ia64: Move part of softmmu slow path out of line, Richard Henderson, 2013/09/06