[Qemu-devel] [PATCH] target-mips: fix decoding of microMIPS POOL32Axf instructions

[Leon Alrae]

These are not DSP instructions, thus there is no "ac" field.

For more details please refer to instruction encoding of
MULT, MULTU, MADD, MADDU, MSUB, MSUBU, MFHI, MFLO, MTHI, MTLO in
MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set

Signed-off-by: Leon Alrae <address@hidden>
---
 target-mips/translate.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index c1d57a7..7451423 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -11113,7 +11113,7 @@ static void gen_pool32axf (CPUMIPSState *env, 
DisasContext *ctx, int rt, int rs)
             mips32_op = OPC_MSUBU;
         do_mul:
             check_insn(ctx, ISA_MIPS32);
-            gen_muldiv(ctx, mips32_op, (ctx->opcode >> 14) & 3, rs, rt);
+            gen_muldiv(ctx, mips32_op, 0, rs, rt);
             break;
         default:
             goto pool32axf_invalid;
@@ -11250,16 +11250,16 @@ static void gen_pool32axf (CPUMIPSState *env, 
DisasContext *ctx, int rt, int rs)
     case 0x35:
         switch (minor & 3) {
         case MFHI32:
-            gen_HILO(ctx, OPC_MFHI, minor >> 2, rs);
+            gen_HILO(ctx, OPC_MFHI, 0, rs);
             break;
         case MFLO32:
-            gen_HILO(ctx, OPC_MFLO, minor >> 2, rs);
+            gen_HILO(ctx, OPC_MFLO, 0, rs);
             break;
         case MTHI32:
-            gen_HILO(ctx, OPC_MTHI, minor >> 2, rs);
+            gen_HILO(ctx, OPC_MTHI, 0, rs);
             break;
         case MTLO32:
-            gen_HILO(ctx, OPC_MTLO, minor >> 2, rs);
+            gen_HILO(ctx, OPC_MTLO, 0, rs);
             break;
         default:
             goto pool32axf_invalid;
-- 
1.7.5.4