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[Qemu-devel] [PULL 4/7] hw/dma/omap_dma: Fix bugs with DMA requests abov
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 4/7] hw/dma/omap_dma: Fix bugs with DMA requests above 32 |
Date: |
Mon, 15 Jul 2013 17:01:32 +0100 |
The drqbmp field of struct soc_dma_s is a uint64_t; however several
places in the code attempt to set bits in it using "(1 << drq)",
which will fail if drq is large enough that the 1 bit gets shifted
off the top of a 32 bit integer. Change these to "(1ULL << drq)" so
that the promotion to 64 bit happens before the shift rather than
afterwards.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
hw/dma/omap_dma.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c
index a81ffc4..0e8cccd 100644
--- a/hw/dma/omap_dma.c
+++ b/hw/dma/omap_dma.c
@@ -248,7 +248,7 @@ static void omap_dma_deactivate_channel(struct omap_dma_s
*s,
/* Don't deactive the channel if it is synchronized and the DMA request is
active */
- if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync)))
+ if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync)))
return;
if (ch->active) {
@@ -268,8 +268,9 @@ static void omap_dma_enable_channel(struct omap_dma_s *s,
/* TODO: theoretically if ch->sync && ch->prefetch &&
* !s->dma->drqbmp[ch->sync], we should also activate and fetch
* from source and then stall until signalled. */
- if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync)))
+ if ((!ch->sync) || (s->dma->drqbmp & (1ULL << ch->sync))) {
omap_dma_activate_channel(s, ch);
+ }
}
}
@@ -1551,12 +1552,12 @@ static void omap_dma_request(void *opaque, int drq, int
req)
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
/* The request pins are level triggered in QEMU. */
if (req) {
- if (~s->dma->drqbmp & (1 << drq)) {
- s->dma->drqbmp |= 1 << drq;
+ if (~s->dma->drqbmp & (1ULL << drq)) {
+ s->dma->drqbmp |= 1ULL << drq;
omap_dma_process_request(s, drq);
}
} else
- s->dma->drqbmp &= ~(1 << drq);
+ s->dma->drqbmp &= ~(1ULL << drq);
}
/* XXX: this won't be needed once soc_dma knows about clocks. */
--
1.7.9.5
- [Qemu-devel] [PULL 0/7] arm-devs queue, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 2/7] hw/cpu/a15mpcore: Correct default value for num-irq, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 1/7] char/cadence_uart: Fix reset for unattached instances, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 7/7] ARM/highbank: add support for Calxeda ECX-2000 / Midway, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 6/7] ARM/highbank: prepare for adding similar machines, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 3/7] sd/pl181.c: Avoid undefined shift behaviour in RWORD macro, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 4/7] hw/dma/omap_dma: Fix bugs with DMA requests above 32,
Peter Maydell <=
- [Qemu-devel] [PULL 5/7] hw/arm/vexpress: Add alias for flash at address 0 on A15 board, Peter Maydell, 2013/07/15