Re: [Qemu-devel] [PATCH qom-cpu v3 30/41] target-openrisc: Move cpu_gdb_{read, write}_register()

[Jia Liu]

Hi Andreas,


On Wed, Jul 10, 2013 at 6:23 AM, Andreas Färber <address@hidden> wrote:
>
> Signed-off-by: Andreas Färber <address@hidden>
> ---
>  gdbstub.c                 | 57 +----------------------------------
>  target-openrisc/gdbstub.c | 77 
> +++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 78 insertions(+), 56 deletions(-)
>  create mode 100644 target-openrisc/gdbstub.c
>
> diff --git a/gdbstub.c b/gdbstub.c
> index 7ee0870..7bcdd3f 100644
> --- a/gdbstub.c
> +++ b/gdbstub.c
> @@ -554,63 +554,8 @@ static int put_packet(GDBState *s, const char *buf)
>
>  #elif defined(TARGET_OPENRISC)
>
> -static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, 
> int n)
> -{
> -    if (n < 32) {
> -        GET_REG32(env->gpr[n]);
> -    } else {
> -        switch (n) {
> -        case 32:    /* PPC */
> -            GET_REG32(env->ppc);
> -
> -        case 33:    /* NPC */
> -            GET_REG32(env->npc);
> -
> -        case 34:    /* SR */
> -            GET_REG32(env->sr);
> -
> -        default:
> -            break;
> -        }
> -    }
> -    return 0;
> -}
> -
> -static int cpu_gdb_write_register(CPUOpenRISCState *env,
> -                                  uint8_t *mem_buf, int n)
> -{
> -    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
> -    CPUClass *cc = CPU_GET_CLASS(cpu);
> -    uint32_t tmp;
> -
> -    if (n > cc->gdb_num_core_regs) {
> -        return 0;
> -    }
> -
> -    tmp = ldl_p(mem_buf);
> -
> -    if (n < 32) {
> -        env->gpr[n] = tmp;
> -    } else {
> -        switch (n) {
> -        case 32: /* PPC */
> -            env->ppc = tmp;
> -            break;
> +#include "target-openrisc/gdbstub.c"
>
> -        case 33: /* NPC */
> -            env->npc = tmp;
> -            break;
> -
> -        case 34: /* SR */
> -            env->sr = tmp;
> -            break;
> -
> -        default:
> -            break;
> -        }
> -    }
> -    return 4;
> -}
>  #elif defined (TARGET_SH4)
>
>  /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
> diff --git a/target-openrisc/gdbstub.c b/target-openrisc/gdbstub.c
> new file mode 100644
> index 0000000..fba096a
> --- /dev/null
> +++ b/target-openrisc/gdbstub.c
> @@ -0,0 +1,77 @@
> +/*
> + * OpenRISC gdb server stub
> + *
> + * Copyright (c) 2003-2005 Fabrice Bellard
> + * Copyright (c) 2013 SUSE LINUX Products GmbH
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see 
> <http://www.gnu.org/licenses/>.
> + */
> +
> +static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, 
> int n)
> +{
> +    if (n < 32) {
> +        GET_REG32(env->gpr[n]);
> +    } else {
> +        switch (n) {
> +        case 32:    /* PPC */
> +            GET_REG32(env->ppc);
> +
> +        case 33:    /* NPC */
> +            GET_REG32(env->npc);
> +
> +        case 34:    /* SR */
> +            GET_REG32(env->sr);
> +
> +        default:
> +            break;
> +        }
> +    }
> +    return 0;
> +}
> +
> +static int cpu_gdb_write_register(CPUOpenRISCState *env,
> +                                  uint8_t *mem_buf, int n)
> +{
> +    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
> +    CPUClass *cc = CPU_GET_CLASS(cpu);
> +    uint32_t tmp;
> +
> +    if (n > cc->gdb_num_core_regs) {
> +        return 0;
> +    }
> +
> +    tmp = ldl_p(mem_buf);
> +
> +    if (n < 32) {
> +        env->gpr[n] = tmp;
> +    } else {
> +        switch (n) {
> +        case 32: /* PPC */
> +            env->ppc = tmp;
> +            break;
> +
> +        case 33: /* NPC */
> +            env->npc = tmp;
> +            break;
> +
> +        case 34: /* SR */
> +            env->sr = tmp;
> +            break;
> +
> +        default:
> +            break;
> +        }
> +    }
> +    return 4;
> +}


Thanks, it looks good to me.

Reviewed-by: Jia Liu <address@hidden>

>
> --
> 1.8.1.4
>

Regards,
Jia