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[Qemu-devel] [PATCH v2 3/5] intc/xilinx_intc: Handle level interrupt ret
From: |
peter . crosthwaite |
Subject: |
[Qemu-devel] [PATCH v2 3/5] intc/xilinx_intc: Handle level interrupt retriggering |
Date: |
Tue, 11 Jun 2013 10:59:09 +1000 |
From: Peter Crosthwaite <address@hidden>
Acking a level sensitive interrupt should have no effect if the
interrupt pin is still asserted. The current implementation requires
and edge condition to occur for setting a level sensitive IRQ, which
means an ACK can clear a level sensitive interrupt, until the original
source strobes the interrupt again.
Fix by keeping track of the interrupt pin state and setting ISR based
on this every time update_irq() is called.
Signed-off-by: Peter Crosthwaite <address@hidden>
---
hw/intc/xilinx_intc.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index a585ba1..010b080 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -49,11 +49,19 @@ struct xlx_pic
/* Runtime control registers. */
uint32_t regs[R_MAX];
+ /* state of the interrupt input pins */
+ uint32_t irq_pin_state;
};
static void update_irq(struct xlx_pic *p)
{
uint32_t i;
+
+ /* level triggered interrupt */
+ if (p->regs[R_MER] & 2) {
+ p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr;
+ }
+
/* Update the pending register. */
p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER];
@@ -139,7 +147,13 @@ static void irq_handler(void *opaque, int irq, int level)
return;
}
- p->regs[R_ISR] |= (level << irq);
+ /* edge triggered interrupt */
+ if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
+ p->regs[R_ISR] |= (level << irq);
+ }
+
+ p->irq_pin_state &= ~(1 << irq);
+ p->irq_pin_state |= level << irq;
update_irq(p);
}
--
1.8.3.rc1.44.gb387c77.dirty
- [Qemu-devel] [PATCH v2 0/5] Xilinx Intc Fixes, peter . crosthwaite, 2013/06/10
- [Qemu-devel] [PATCH v2 1/5] microblaze/petalogix_s3adsp1800_mmu: Fix UART IRQ, peter . crosthwaite, 2013/06/10
- [Qemu-devel] [PATCH v2 2/5] intc/xilinx_intc: Don't clear level sens. IRQs without ACK, peter . crosthwaite, 2013/06/10
- [Qemu-devel] [PATCH v2 3/5] intc/xilinx_intc: Handle level interrupt retriggering,
peter . crosthwaite <=
- [Qemu-devel] [PATCH v2 4/5] intc/xilinx_intc: Inhibit write to ISR when HIE, peter . crosthwaite, 2013/06/10
- [Qemu-devel] [PATCH v2 5/5] intc/xilinx_intc: Dont lower IRQ when HIE cleared, peter . crosthwaite, 2013/06/10
- Re: [Qemu-devel] [PATCH v2 0/5] Xilinx Intc Fixes, Edgar E. Iglesias, 2013/06/18