[Qemu-devel] [PATCH v3 0/5] Data Driven device registers & Zynq DEVCFG

[peter . crosthwaite]

From: Peter Crosthwaite <address@hidden>

Hi All. This is a new scheme i've come up with handling device registers in a
data driven way. My motivation for this is to factor out a lot of the access
checking that seems to be replicated in every device. See P2 commit message for
further discussion.

P1 is a trivial addition to bitops.h
P2 is the main patch, adds the register definition functionality
P3 adds helpers that glue the register API to the Memory API
P4 is an example new device (the Xilinx Zynq devcfg) that uses this scheme.
P5 adds devcfg to the Zynq machine model

This devcfg device was particularly finnicky with per-bit restrictions which
prompted all this. I'm also looking for a higher-than-usual modelling fidelity
on the register space, with semantics defined for random reserved bits
in-between otherwise consistent fields.

Heres an example of the qemu_log output for the devcfg device. This is produced
by now generic sharable code:

/machine/unattached/device[44]:Addr 0x000008:CFG: write of value 00000508
/machine/unattached/device[44]:Addr 0x000080:MCTRL: write of value 00800010
/machine/unattached/device[44]:Addr 0x000010:INT_MASK: write of value ffffffff
/machine/unattached/device[44]:Addr 00000000:CTRL: write of value 0c00607f

And an example of a rogue guest banging on a bad bit:

/machine/unattached/device[44]:Addr 0x000014:STATUS bits 0x000001 may not be \
                                                                written to 1

Future work: Theres a lot of overlap here with what Peter did with the ARM
coprocessor definitions. We could go further and generalise ARM CP to use this
or some further evolution of it. That and converting existing models to this
scheme. Some device models will lose a lot of weight.

Changed from v2:
Fixed for hw/ re-orginisation (Paolo review)
Simplified and optimized (PMM and Gerd review)
Changed from v1:
Added ONES macro patch
Dropped bogus former patch 1 (PMM review)
Addressed Blue, Gerd and MST comments.
Simplified to be more Memory API compatible.
Added Memory API helpers.
Please see discussion already on list and commit msgs for more detail.


Peter A. G. Crosthwaite (2):
  xilinx_devcfg: Zynq devcfg device model
  xilinx_zynq: added devcfg to machine model

Peter Crosthwaite (3):
  bitops: Add ONES macro
  register: Add Register API
  register: Add Memory API glue

 default-configs/arm-softmmu.mak |   1 +
 hw/arm/xilinx_zynq.c            |   8 +
 hw/core/Makefile.objs           |   1 +
 hw/core/register.c              | 238 +++++++++++++++++++
 hw/dma/Makefile.objs            |   1 +
 hw/dma/xilinx_devcfg.c          | 495 ++++++++++++++++++++++++++++++++++++++++
 include/hw/register.h           | 141 ++++++++++++
 include/qemu/bitops.h           |   2 +
 8 files changed, 887 insertions(+)
 create mode 100644 hw/core/register.c
 create mode 100644 hw/dma/xilinx_devcfg.c
 create mode 100644 include/hw/register.h

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1.8.3.rc1.44.gb387c77.dirty