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[Qemu-devel] [PATCH 06/12] target-i386/helper: remove ESP macro
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From: |
liguang |
|
Subject: |
[Qemu-devel] [PATCH 06/12] target-i386/helper: remove ESP macro |
|
Date: |
Mon, 22 Apr 2013 11:33:24 +0800 |
Signed-off-by: liguang <address@hidden>
---
target-i386/cpu.h | 2 -
target-i386/seg_helper.c | 80 +++++++++++++++++++++++----------------------
target-i386/smm_helper.c | 8 ++--
target-i386/svm_helper.c | 8 ++--
4 files changed, 49 insertions(+), 49 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index f2c4a49..9d52939 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1107,8 +1107,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
}
-#undef ESP
-#define ESP (env->regs[R_ESP])
#undef ESI
#define ESI (env->regs[R_ESI])
#undef EDI
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 56db00f..f8115d1 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -328,7 +328,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
- cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP);
+ cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), ESI);
cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), EDI);
@@ -344,7 +344,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
- cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP);
+ cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), ESI);
cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), EDI);
@@ -400,7 +400,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
env->regs[R_ECX] = new_regs[1];
env->regs[R_EDX] = new_regs[2];
env->regs[R_EBX] = new_regs[3];
- ESP = new_regs[4];
+ env->regs[R_ESP] = new_regs[4];
env->regs[R_EBP] = new_regs[5];
ESI = new_regs[6];
EDI = new_regs[7];
@@ -505,17 +505,19 @@ static int exception_has_error_code(int intno)
#define SET_ESP(val, sp_mask) \
do { \
if ((sp_mask) == 0xffff) { \
- ESP = (ESP & ~0xffff) | ((val) & 0xffff); \
- } else if ((sp_mask) == 0xffffffffLL) { \
- ESP = (uint32_t)(val); \
- } else { \
- ESP = (val); \
- } \
+ env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
+ ((val) & 0xffff); \
+ } else if ((sp_mask) == 0xffffffffLL) { \
+ env->regs[R_ESP] = (uint32_t)(val); \
+ } else { \
+ env->regs[R_ESP] = (val); \
+ } \
} while (0)
#else
#define SET_ESP(val, sp_mask) \
do { \
- ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask)); \
+ env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \
+ ((val) & (sp_mask)); \
} while (0)
#endif
@@ -598,7 +600,7 @@ static void do_interrupt_protected(CPUX86State *env, int
intno, int is_int,
} else {
mask = 0xffff;
}
- esp = (ESP - (2 << shift)) & mask;
+ esp = (env->regs[R_ESP] - (2 << shift)) & mask;
ssp = env->segs[R_SS].base + esp;
if (shift) {
cpu_stl_kernel(env, ssp, error_code);
@@ -680,7 +682,7 @@ static void do_interrupt_protected(CPUX86State *env, int
intno, int is_int,
new_stack = 0;
sp_mask = get_sp_mask(env->segs[R_SS].flags);
ssp = env->segs[R_SS].base;
- esp = ESP;
+ esp = env->regs[R_ESP];
dpl = cpl;
} else {
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
@@ -709,7 +711,7 @@ static void do_interrupt_protected(CPUX86State *env, int
intno, int is_int,
PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
}
PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
- PUSHL(ssp, esp, sp_mask, ESP);
+ PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]);
}
PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
@@ -726,7 +728,7 @@ static void do_interrupt_protected(CPUX86State *env, int
intno, int is_int,
PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
}
PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
- PUSHW(ssp, esp, sp_mask, ESP);
+ PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]);
}
PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
@@ -888,7 +890,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int
is_int,
if (ist != 0) {
esp = get_rsp_from_tss(env, ist + 3);
} else {
- esp = ESP;
+ esp = env->regs[R_ESP];
}
esp &= ~0xfLL; /* align stack */
dpl = cpl;
@@ -899,7 +901,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int
is_int,
}
PUSHQ(esp, env->segs[R_SS].selector);
- PUSHQ(esp, ESP);
+ PUSHQ(esp, env->regs[R_ESP]);
PUSHQ(esp, cpu_compute_eflags(env));
PUSHQ(esp, env->segs[R_CS].selector);
PUSHQ(esp, old_eip);
@@ -911,7 +913,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int
is_int,
ss = 0 | dpl;
cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
}
- ESP = esp;
+ env->regs[R_ESP] = esp;
selector = (selector & ~3) | dpl;
cpu_x86_load_seg_cache(env, R_CS, selector,
@@ -1069,7 +1071,7 @@ static void do_interrupt_real(CPUX86State *env, int
intno, int is_int,
ptr = dt->base + intno * 4;
offset = cpu_lduw_kernel(env, ptr);
selector = cpu_lduw_kernel(env, ptr + 2);
- esp = ESP;
+ esp = env->regs[R_ESP];
ssp = env->segs[R_SS].base;
if (is_int) {
old_eip = next_eip;
@@ -1083,7 +1085,7 @@ static void do_interrupt_real(CPUX86State *env, int
intno, int is_int,
PUSHW(ssp, esp, 0xffff, old_eip);
/* update processor state */
- ESP = (ESP & ~0xffff) | (esp & 0xffff);
+ env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff);
env->eip = offset;
env->segs[R_CS].selector = selector;
env->segs[R_CS].base = (selector << 4);
@@ -1171,7 +1173,7 @@ static void do_interrupt_all(CPUX86State *env, int intno,
int is_int,
env->hflags & HF_CPL_MASK,
env->segs[R_CS].selector, EIP,
(int)env->segs[R_CS].base + EIP,
- env->segs[R_SS].selector, ESP);
+ env->segs[R_SS].selector, env->regs[R_ESP]);
if (intno == 0x0e) {
qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
} else {
@@ -1273,7 +1275,7 @@ void helper_enter_level(CPUX86State *env, int level, int
data32,
esp_mask = get_sp_mask(env->segs[R_SS].flags);
ssp = env->segs[R_SS].base;
ebp = env->regs[R_EBP];
- esp = ESP;
+ esp = env->regs[R_ESP];
if (data32) {
/* 32 bit */
esp -= 4;
@@ -1306,7 +1308,7 @@ void helper_enter64_level(CPUX86State *env, int level,
int data64,
target_ulong esp, ebp;
ebp = env->regs[R_EBP];
- esp = ESP;
+ esp = env->regs[R_ESP];
if (data64) {
/* 64 bit */
@@ -1653,7 +1655,7 @@ void helper_lcall_real(CPUX86State *env, int new_cs,
target_ulong new_eip1,
target_ulong ssp;
new_eip = new_eip1;
- esp = ESP;
+ esp = env->regs[R_ESP];
esp_mask = get_sp_mask(env->segs[R_SS].flags);
ssp = env->segs[R_SS].base;
if (shift) {
@@ -1721,11 +1723,11 @@ void helper_lcall_protected(CPUX86State *env, int
new_cs, target_ulong new_eip,
target_ulong rsp;
/* 64 bit case */
- rsp = ESP;
+ rsp = env->regs[R_ESP];
PUSHQ(rsp, env->segs[R_CS].selector);
PUSHQ(rsp, next_eip);
/* from this point, not restartable */
- ESP = rsp;
+ env->regs[R_ESP] = rsp;
cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
get_seg_base(e1, e2),
get_seg_limit(e1, e2), e2);
@@ -1733,7 +1735,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs,
target_ulong new_eip,
} else
#endif
{
- sp = ESP;
+ sp = env->regs[R_ESP];
sp_mask = get_sp_mask(env->segs[R_SS].flags);
ssp = env->segs[R_SS].base;
if (shift) {
@@ -1809,9 +1811,9 @@ void helper_lcall_protected(CPUX86State *env, int new_cs,
target_ulong new_eip,
if (!(e2 & DESC_C_MASK) && dpl < cpl) {
/* to inner privilege */
get_ss_esp_from_tss(env, &ss, &sp, dpl);
- LOG_PCALL("new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx
+ LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
TARGET_FMT_lx
"\n",
- ss, sp, param_count, ESP);
+ ss, sp, param_count, env->regs[R_ESP]);
if ((ss & 0xfffc) == 0) {
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
}
@@ -1843,17 +1845,17 @@ void helper_lcall_protected(CPUX86State *env, int
new_cs, target_ulong new_eip,
ssp = get_seg_base(ss_e1, ss_e2);
if (shift) {
PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
- PUSHL(ssp, sp, sp_mask, ESP);
+ PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]);
for (i = param_count - 1; i >= 0; i--) {
- val = cpu_ldl_kernel(env, old_ssp + ((ESP + i * 4) &
+ val = cpu_ldl_kernel(env, old_ssp + ((env->regs[R_ESP] + i
* 4) &
old_sp_mask));
PUSHL(ssp, sp, sp_mask, val);
}
} else {
PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
- PUSHW(ssp, sp, sp_mask, ESP);
+ PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]);
for (i = param_count - 1; i >= 0; i--) {
- val = cpu_lduw_kernel(env, old_ssp + ((ESP + i * 2) &
+ val = cpu_lduw_kernel(env, old_ssp + ((env->regs[R_ESP] +
i * 2) &
old_sp_mask));
PUSHW(ssp, sp, sp_mask, val);
}
@@ -1861,7 +1863,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs,
target_ulong new_eip,
new_stack = 1;
} else {
/* to same privilege */
- sp = ESP;
+ sp = env->regs[R_ESP];
sp_mask = get_sp_mask(env->segs[R_SS].flags);
ssp = env->segs[R_SS].base;
/* push_size = (4 << shift); */
@@ -1905,7 +1907,7 @@ void helper_iret_real(CPUX86State *env, int shift)
int eflags_mask;
sp_mask = 0xffff; /* XXXX: use SS segment size? */
- sp = ESP;
+ sp = env->regs[R_ESP];
ssp = env->segs[R_SS].base;
if (shift == 1) {
/* 32 bits */
@@ -1919,7 +1921,7 @@ void helper_iret_real(CPUX86State *env, int shift)
POPW(ssp, sp, sp_mask, new_cs);
POPW(ssp, sp, sp_mask, new_eflags);
}
- ESP = (ESP & ~sp_mask) | (sp & sp_mask);
+ env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask);
env->segs[R_CS].selector = new_cs;
env->segs[R_CS].base = (new_cs << 4);
env->eip = new_eip;
@@ -1978,7 +1980,7 @@ static inline void helper_ret_protected(CPUX86State *env,
int shift,
{
sp_mask = get_sp_mask(env->segs[R_SS].flags);
}
- sp = ESP;
+ sp = env->regs[R_ESP];
ssp = env->segs[R_SS].base;
new_eflags = 0; /* avoid warning */
#ifdef TARGET_X86_64
@@ -2179,7 +2181,7 @@ static inline void helper_ret_protected(CPUX86State *env,
int shift,
load_seg_vm(env, R_GS, new_gs & 0xffff);
env->eip = new_eip & 0xffff;
- ESP = new_esp;
+ env->regs[R_ESP] = new_esp;
}
void helper_iret_protected(CPUX86State *env, int shift, int next_eip)
@@ -2248,7 +2250,7 @@ void helper_sysenter(CPUX86State *env)
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
DESC_S_MASK |
DESC_W_MASK | DESC_A_MASK);
- ESP = env->sysenter_esp;
+ env->regs[R_ESP] = env->sysenter_esp;
EIP = env->sysenter_eip;
}
@@ -2288,7 +2290,7 @@ void helper_sysexit(CPUX86State *env, int dflag)
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
DESC_W_MASK | DESC_A_MASK);
}
- ESP = env->regs[R_ECX];
+ env->regs[R_ESP] = env->regs[R_ECX];
EIP = env->regs[R_EDX];
}
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 4bd73eb..50c5d99 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -86,7 +86,7 @@ void do_smm_enter(CPUX86State *env)
stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]);
stq_phys(sm_state + 0x7fe8, env->regs[R_EDX]);
stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
- stq_phys(sm_state + 0x7fd8, ESP);
+ stq_phys(sm_state + 0x7fd8, env->regs[R_ESP]);
stq_phys(sm_state + 0x7fd0, env->regs[R_EBP]);
stq_phys(sm_state + 0x7fc8, ESI);
stq_phys(sm_state + 0x7fc0, EDI);
@@ -112,7 +112,7 @@ void do_smm_enter(CPUX86State *env)
stl_phys(sm_state + 0x7fec, EDI);
stl_phys(sm_state + 0x7fe8, ESI);
stl_phys(sm_state + 0x7fe4, env->regs[R_EBP]);
- stl_phys(sm_state + 0x7fe0, ESP);
+ stl_phys(sm_state + 0x7fe0, env->regs[R_ESP]);
stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
stl_phys(sm_state + 0x7fd8, env->regs[R_EDX]);
stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]);
@@ -217,7 +217,7 @@ void helper_rsm(CPUX86State *env)
env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0);
env->regs[R_EDX] = ldq_phys(sm_state + 0x7fe8);
env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
- ESP = ldq_phys(sm_state + 0x7fd8);
+ env->regs[R_ESP] = ldq_phys(sm_state + 0x7fd8);
env->regs[R_EBP] = ldq_phys(sm_state + 0x7fd0);
ESI = ldq_phys(sm_state + 0x7fc8);
EDI = ldq_phys(sm_state + 0x7fc0);
@@ -247,7 +247,7 @@ void helper_rsm(CPUX86State *env)
EDI = ldl_phys(sm_state + 0x7fec);
ESI = ldl_phys(sm_state + 0x7fe8);
env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4);
- ESP = ldl_phys(sm_state + 0x7fe0);
+ env->regs[R_ESP] = ldl_phys(sm_state + 0x7fe0);
env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8);
env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index b59a2ca..5706026 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -171,7 +171,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int
next_eip_addend)
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip),
EIP + next_eip_addend);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp), ESP);
+ stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp),
env->regs[R_ESP]);
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax),
env->regs[R_EAX]);
/* load the interception bitmaps so we do not need to access the
@@ -250,7 +250,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int
next_eip_addend)
EIP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
env->eip = EIP;
- ESP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
+ env->regs[R_ESP] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
save.rsp));
env->regs[R_EAX] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
save.rax));
env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));
env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6));
@@ -606,7 +606,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code,
uint64_t exit_info_1)
cpu_compute_eflags(env));
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip),
env->eip);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), ESP);
+ stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
@@ -658,7 +658,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code,
uint64_t exit_info_1)
R_DS);
EIP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
- ESP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
+ env->regs[R_ESP] = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.rsp));
env->regs[R_EAX] = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.rax));
env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
--
1.7.2.5
- [Qemu-devel] [PATCH 06/12] target-i386/helper: remove ESP macro, (continued)
- [Qemu-devel] [PATCH 06/12] target-i386/helper: remove ESP macro, liguang, 2013/04/21
- [Qemu-devel] [PATCH 00/11] target-i386: remove some macros, liguang, 2013/04/21
- [Qemu-devel] [PATCH 02/12] target-i386/helper: remove EBX macro, liguang, 2013/04/21
- [Qemu-devel] [PATCH 05/12] target-i386/helper: remove EBP macro, liguang, 2013/04/21
- [Qemu-devel] [PATCH 12/12] target-i386: fix over 80 chars warnings, liguang, 2013/04/21
- [Qemu-devel] [PATCH 10/12] target-i386/helper: remove DF macro, liguang, 2013/04/21
- [Qemu-devel] [PATCH 11/12] target-i386/helper: remove redundant env->eip assignment, liguang, 2013/04/21
- [Qemu-devel] [PATCH 08/12] target-i386/helper: remove EDI macro, liguang, 2013/04/21
- [Qemu-devel] [PATCH 07/12] target-i386/helper: remove ESI macro, liguang, 2013/04/21
- [Qemu-devel] [PATCH 03/12] target-i386/helper: remove ECX macro, liguang, 2013/04/21
- [Qemu-devel] [PATCH 06/12] target-i386/helper: remove ESP macro,
liguang <=
- [Qemu-devel] [PATCH 09/12] target-i386/helper: remove EIP macro, liguang, 2013/04/21
- [Qemu-devel] [PATCH 01/12] target-i386/helper: remove EAX macro, liguang, 2013/04/22
- [Qemu-devel] [PATCH 04/12] target-i386/helper: remove EDX macro, liguang, 2013/04/22