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[Qemu-devel] [PATCH for-1.5 v2 10/15] xilinx_spips: Fix CTRL register RW
From: |
peter . crosthwaite |
Subject: |
[Qemu-devel] [PATCH for-1.5 v2 10/15] xilinx_spips: Fix CTRL register RW bits |
Date: |
Fri, 19 Apr 2013 12:09:31 +1000 |
From: Peter Crosthwaite <address@hidden>
The CTRL register was RAZ/WI on some of the RW bits. Even though the
function behind these bits is invalid in QEMU, they should still be
guest accessible. Fix.
Signed-off-by: Peter Crosthwaite <address@hidden>
---
changed from v1
Macroified magic number (PMM review)
hw/ssi/xilinx_spips.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index bc86375..b5997c1 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -56,6 +56,7 @@
#define CLK_PH (1 << 2)
#define CLK_POL (1 << 1)
#define MODE_SEL (1 << 0)
+#define R_CONFIG_RSVD (0x7bf40000)
/* interrupt mechanism */
#define R_INTR_STATUS (0x04 / 4)
@@ -355,7 +356,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
addr >>= 2;
switch (addr) {
case R_CONFIG:
- mask = 0x0002FFFF;
+ mask = ~(R_CONFIG_RSVD | MAN_START_COM);
break;
case R_INTR_STATUS:
ret = s->regs[addr] & IXR_ALL;
@@ -415,7 +416,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
addr >>= 2;
switch (addr) {
case R_CONFIG:
- mask = 0x0002FFFF;
+ mask = ~(R_CONFIG_RSVD | MAN_START_COM);
if (value & MAN_START_COM) {
man_start_com = 1;
}
--
1.7.0.4
- [Qemu-devel] [PATCH for-1.5 v2 01/15] xilinx_spips: seperate SPI and QSPI as two classes, (continued)
- [Qemu-devel] [PATCH for-1.5 v2 01/15] xilinx_spips: seperate SPI and QSPI as two classes, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 02/15] xilinx_spips: Make interrupts clear on read, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 03/15] xilinx_spips: Inhibit interrupts in LQSPI mode, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 04/15] xilinx_spips: Add verbose LQSPI debug output, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 05/15] xilinx_spips: Fix QSPI FIFO size, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 06/15] xilinx_spips: Trash LQ page cache on mode change, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 07/15] xilinx_spips: Add automatic start support, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 08/15] xilinx_spips: Implement automatic CS, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 09/15] xilinx_spips: lqspi: Dont touch config register, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 10/15] xilinx_spips: Fix CTRL register RW bits,
peter . crosthwaite <=
- [Qemu-devel] [PATCH for-1.5 v2 11/15] xilinx_spips: Fix striping behaviour, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 12/15] xilinx_spips: Debug msgs for Snoop state, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 13/15] xilinx_spips: Multiple debug verbosity levels, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 14/15] xilinx_spips: lqspi: Push more data to tx-fifo, peter . crosthwaite, 2013/04/18
- [Qemu-devel] [PATCH for-1.5 v2 15/15] xilinx_spips: lqspi: Fix byte/misaligned access, peter . crosthwaite, 2013/04/18
- Re: [Qemu-devel] [PATCH for-1.5 v2 00/15] Xilinx SPIPS fixes round 2, Peter Maydell, 2013/04/19