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[Qemu-devel] [PATCH v5 32/33] tcg-ppc64: Implement mulu2/muls2_i64
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v5 32/33] tcg-ppc64: Implement mulu2/muls2_i64 |
Date: |
Mon, 15 Apr 2013 20:41:11 +0200 |
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ppc64/tcg-target.c | 27 +++++++++++++++++++++++++++
tcg/ppc64/tcg-target.h | 4 ++--
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 1018266..0f33583 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1988,6 +1988,31 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc,
const TCGArg *args,
}
break;
+ case INDEX_op_mulu2_i64:
+ case INDEX_op_muls2_i64:
+ {
+ int oph = (opc == INDEX_op_mulu2_i64 ? MULHDU : MULHD);
+ TCGReg outl = args[0], outh = args[1];
+ a0 = args[2], a1 = args[3];
+
+ if (outl == a0 || outl == a1) {
+ if (outh == a0 || outh == a1) {
+ outl = TCG_REG_R0;
+ } else {
+ tcg_out32(s, oph | TAB(outh, a0, a1));
+ oph = 0;
+ }
+ }
+ tcg_out32(s, MULLD | TAB(outl, a0, a1));
+ if (oph != 0) {
+ tcg_out32(s, oph | TAB(outh, a0, a1));
+ }
+ if (outl != args[0]) {
+ tcg_out_mov(s, TCG_TYPE_I64, args[0], outl);
+ }
+ }
+ break;
+
default:
tcg_dump_ops (s);
tcg_abort ();
@@ -2116,6 +2141,8 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_add2_i64, { "r", "r", "r", "rI", "r", "rZM" } },
{ INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },
+ { INDEX_op_muls2_i64, { "r", "r", "r", "r" } },
+ { INDEX_op_mulu2_i64, { "r", "r", "r", "r" } },
{ -1 },
};
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 8dff1d5..cb77634 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -114,8 +114,8 @@ typedef enum {
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
-#define TCG_TARGET_HAS_mulu2_i64 0
-#define TCG_TARGET_HAS_muls2_i64 0
+#define TCG_TARGET_HAS_mulu2_i64 1
+#define TCG_TARGET_HAS_muls2_i64 1
#define TCG_AREG0 TCG_REG_R27
--
1.8.1.4
- [Qemu-devel] [PATCH v5 20/33] tcg-ppc64: Implement bswap64, (continued)
- [Qemu-devel] [PATCH v5 20/33] tcg-ppc64: Implement bswap64, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 22/33] tcg-ppc64: Handle constant inputs for some compound logicals, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 23/33] tcg-ppc64: Implement deposit, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 24/33] tcg-ppc64: Use I constraint for mul, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 25/33] tcg-ppc64: Use TCGType throughout compares, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 26/33] tcg-ppc64: Cleanup i32 constants to tcg_out_cmp, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 27/33] tcg-ppc64: Use MFOCRF instead of MFCR, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 28/33] tcg-ppc64: Use ISEL for setcond, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 30/33] tcg-ppc64: Use getauxval for ISA detection, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 31/33] tcg-ppc64: Implement add2/sub2_i64, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 32/33] tcg-ppc64: Implement mulu2/muls2_i64,
Richard Henderson <=
- [Qemu-devel] [PATCH v5 33/33] tcg-ppc64: Handle deposit of zero, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 29/33] tcg-ppc64: Implement movcond, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 21/33] tcg-ppc64: Implement compound logicals, Richard Henderson, 2013/04/15
- Re: [Qemu-devel] [PATCH v5 00/33] Modernize tcg/ppc64, Aurelien Jarno, 2013/04/15