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[Qemu-devel] [PATCH 09/10] target-i386: enable SSE4.1 and SSE4.2 in TCG
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 09/10] target-i386: enable SSE4.1 and SSE4.2 in TCG mode |
Date: |
Tue, 26 Mar 2013 20:01:41 +0100 |
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-i386/cpu.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index a0640db..4b43759 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -388,16 +388,17 @@ typedef struct x86_def_t {
/* missing:
CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
- CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
- CPUID_EXT_MOVBE | CPUID_EXT_HYPERVISOR)
+ CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | \
+ CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | \
+ CPUID_EXT_HYPERVISOR)
/* missing:
CPUID_EXT_PCLMULQDQ, CPUID_EXT_DTES64, CPUID_EXT_DSCPL,
CPUID_EXT_VMX, CPUID_EXT_SMX, CPUID_EXT_EST, CPUID_EXT_TM2,
CPUID_EXT_CID, CPUID_EXT_FMA, CPUID_EXT_XTPR, CPUID_EXT_PDCM,
- CPUID_EXT_PCID, CPUID_EXT_DCA, CPUID_EXT_SSE41, CPUID_EXT_SSE42,
- CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AES,
- CPUID_EXT_XSAVE, CPUID_EXT_OSXSAVE, CPUID_EXT_AVX,
- CPUID_EXT_F16C, CPUID_EXT_RDRAND */
+ CPUID_EXT_PCID, CPUID_EXT_DCA, CPUID_EXT_X2APIC,
+ CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AES, CPUID_EXT_XSAVE,
+ CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
+ CPUID_EXT_RDRAND */
#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
--
1.7.10.4
- [Qemu-devel] [PATCH 08/10] target-i386: SSE4.2: fix pcmpXstrX instructions with "Masked(-)" polarity, (continued)
- [Qemu-devel] [PATCH 08/10] target-i386: SSE4.2: fix pcmpXstrX instructions with "Masked(-)" polarity, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 05/10] target-i386: SSE4.2: fix pcmpXstrX instructions in "Ranges" mode, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 03/10] target-i386: SSE4.2: fix pcmpXstri instructions, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 04/10] target-i386: SSE4.2: fix pcmpXstrm instructions, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 02/10] target-i386: SSE4.2: fix pcmpgtq instruction, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 09/10] target-i386: enable SSE4.1 and SSE4.2 in TCG mode,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 10/10] target-i386: SSE4.2: use clz32/ctz32 instead of reinventing the wheel, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 06/10] target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal each" mode, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 01/10] target-i386: SSE4.1: fix pinsrb instruction, Aurelien Jarno, 2013/03/26
- [Qemu-devel] [PATCH 07/10] target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal ordered" mode, Aurelien Jarno, 2013/03/26