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[Qemu-devel] Cortex-M4F Floating Point system registers
From: |
Fabien Chouteau |
Subject: |
[Qemu-devel] Cortex-M4F Floating Point system registers |
Date: |
Wed, 20 Mar 2013 17:05:10 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130308 Thunderbird/17.0.4 |
Hello QEMU ARM folks,
I'm looking at the ARMv7-M profile and the implementation in QEMU.
Looks like M3 is supported and I'd like to work on M4F (FP context save
and lazy FP context save).
I wonder how the FPU system registers, and more generally how the
co-processor registers are implemented in QEMU.
For example in the Cortex-M4 TRM it seems like FP system registers are
mapped in memory. I don't see that implemented in QEMU.
Thanks,
--
Fabien Chouteau
- [Qemu-devel] Cortex-M4F Floating Point system registers,
Fabien Chouteau <=