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[Qemu-devel] [PATCH 27/38] target-ppc: Compute addition overflow without
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 27/38] target-ppc: Compute addition overflow without branches |
Date: |
Tue, 19 Feb 2013 23:52:15 -0800 |
Cc: Alexander Graf <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-ppc/translate.c | 46 +++++++++++++---------------------------------
1 file changed, 13 insertions(+), 33 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7aab6ae..116cf12 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -746,35 +746,23 @@ static void gen_isel(DisasContext *ctx)
static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
TCGv arg1, TCGv arg2, int sub)
{
- int l1;
- TCGv t0;
+ TCGv t0 = tcg_temp_new();
- l1 = gen_new_label();
- /* Start with XER OV disabled, the most likely case */
- tcg_gen_movi_tl(cpu_ov, 0);
- t0 = tcg_temp_local_new();
- tcg_gen_xor_tl(t0, arg0, arg1);
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode)
- tcg_gen_ext32s_tl(t0, t0);
-#endif
- if (sub)
- tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
- else
- tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
+ tcg_gen_xor_tl(cpu_ov, arg0, arg1);
tcg_gen_xor_tl(t0, arg1, arg2);
+ if (sub) {
+ tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
+ } else {
+ tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
+ }
+ tcg_temp_free(t0);
#if defined(TARGET_PPC64)
- if (!ctx->sf_mode)
- tcg_gen_ext32s_tl(t0, t0);
+ if (!ctx->sf_mode) {
+ tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
+ }
#endif
- if (sub)
- tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
- else
- tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
- tcg_gen_movi_tl(cpu_ov, 1);
- tcg_gen_movi_tl(cpu_so, 1);
- gen_set_label(l1);
- tcg_temp_free(t0);
+ tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
+ tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
@@ -837,10 +825,6 @@ static inline void gen_op_arith_add(DisasContext *ctx,
TCGv ret, TCGv arg1,
/* Start with XER CA disabled, the most likely case */
tcg_gen_movi_tl(cpu_ca, 0);
}
- if (compute_ov) {
- /* Start with XER OV disabled, the most likely case */
- tcg_gen_movi_tl(cpu_ov, 0);
- }
tcg_gen_add_tl(t0, arg1, arg2);
@@ -1261,10 +1245,6 @@ static inline void gen_op_arith_subf(DisasContext *ctx,
TCGv ret, TCGv arg1,
/* Start with XER CA disabled, the most likely case */
tcg_gen_movi_tl(cpu_ca, 0);
}
- if (compute_ov) {
- /* Start with XER OV disabled, the most likely case */
- tcg_gen_movi_tl(cpu_ov, 0);
- }
if (add_ca) {
tcg_gen_not_tl(t0, arg1);
--
1.8.1.2
- [Qemu-devel] [PATCH 30/38] target-ppc: Implement neg in terms of subf, (continued)
- [Qemu-devel] [PATCH 30/38] target-ppc: Implement neg in terms of subf, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 36/38] target-unicore32: Use mul*2 for do_mult, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 24/38] target-ppc: Use mul*2 in mulh* insns, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 20/38] target-arm: Implement adc_cc inline, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 37/38] target-xtensa: Use mul*2 for mul*hi, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 35/38] target-sh4: Use mul*2 for dmul*, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 31/38] target-ppc: Compute arithmetic shift carry without branches, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 29/38] target-ppc: Use add2 for carry generation, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 19/38] target-arm: Use add2 in gen_add_CC, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 27/38] target-ppc: Compute addition overflow without branches,
Richard Henderson <=
- [Qemu-devel] [PATCH 22/38] target-mips: Use mul[us]2 in [D]MULT[U] insns, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 23/38] target-cris: Use mul*2 in mul* insns, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 25/38] target-ppc: Split out SO, OV, CA fields from XER, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 17/38] target-arm: Use mul[us]2 in gen_mul[us]_i64_i32, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 38/38] target-xtensa: Use add2/sub2 for mac, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 26/38] target-ppc: Use setcond in gen_op_cmp, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 21/38] target-arm: Implement sbc_cc inline, Richard Henderson, 2013/02/20
- Re: [Qemu-devel] [PATCH 00/38] Add double-word addition and widening multiply tcg ops, Blue Swirl, 2013/02/23