Re: [Qemu-devel] [PATCH v3] PIIX3: reset the VM when the Reset Control Register's RCPU bit gets set

[Paolo Bonzini]

Il 19/02/2013 15:57, Laszlo Ersek ha scritto:
>> > 
>> > You can find it in the ICH9 spec on page 486
>> > (http://www.intel.com/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf).
> (Thanks for the link. Interestingly, "wget" got "403 Forbidden". I
> googled the filename and then found it under the exact same URL. Intel's
> webserver probably insists on a cookie or some Referer.)
> 
> ... earlier Michael pointed out to me that a shared handler for the
> [0xcf8, 0xcfc) range would be preferred over the overlapping regions.
> (Which makes me recall my RFC version of the patch.) Since RST_CNT on
> the ICH9 is also at 0xcf9, I assume I should fix up the PIIX3 first and
> then follow the PIIX3 impl. in ICH9.

I actually thought the same, but it is really weird how it works in real
hardware.

0xCF8 and 0xCFC are handled by the PCI host (part of the i440FX aka
NorthBridge), while 0xCF9 are handled by PIIX3.  You cannot find 0xCF8
and 0xCFC in the PIIX3 and ICH9 datasheets, you cannot find 0xCF9 in the
i440FX datasheet (didn't check Q35).

So it looks like these are _really_ overlapping regions in hardware.

> I could even attempt adding the "hard reset out" thing you mention in
> <http://thread.gmane.org/gmane.comp.emulators.qemu/195351/focus=195358>.
> (Full emulation of PCIRST# seems "slightly" complex... :))

David beat you to that. :)

Paolo

> Michael, what do you think? :)