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[Qemu-devel] [PATCH 27/60] x86: Fixed incorrect segment base address add
From: |
Michael Tokarev |
Subject: |
[Qemu-devel] [PATCH 27/60] x86: Fixed incorrect segment base address addition in 64-bits mode |
Date: |
Mon, 4 Feb 2013 14:40:37 +0400 |
From: Vitaly Chipounov <address@hidden>
According to the Intel manual
"Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 3", "3.4.4 Segment Loading Instructions in IA-32e Mode":
"When in compatibility mode, FS and GS overrides operate as defined by
32-bit mode behavior regardless of the value loaded into the upper 32
linear-address bits of the hidden descriptor register base field.
Compatibility mode ignores the upper 32 bits when calculating an effective
address."
However, the code misses the 64-bit mode case, where an instruction with
address and segment size override would be translated incorrectly. For example,
inc dword ptr gs:260h[ebx*4] gets incorrectly translated to:
(uint32_t)(gs.base + ebx * 4 + 0x260)
instead of
gs.base + (uint32_t)(ebx * 4 + 0x260)
Signed-off-by: Vitaly Chipounov <address@hidden>
Reviewed-by: Max Filippov <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>
(cherry picked from commit 7162ab21fe8e82f924002951cd8e87f69358f8b5)
Signed-off-by: Michael Tokarev <address@hidden>
---
target-i386/translate.c | 43 +++++++++++++++++++++++++------------------
1 file changed, 25 insertions(+), 18 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c792e7a..7c69ec0 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -456,12 +456,19 @@ static inline void gen_op_movl_A0_seg(int reg)
tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) +
REG_L_OFFSET);
}
-static inline void gen_op_addl_A0_seg(int reg)
+static inline void gen_op_addl_A0_seg(DisasContext *s, int reg)
{
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
#ifdef TARGET_X86_64
- tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
+ if (CODE64(s)) {
+ tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
+ tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
+ } else {
+ tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
+ tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
+ }
+#else
+ tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
#endif
}
@@ -617,7 +624,7 @@ static inline void gen_string_movl_A0_ESI(DisasContext *s)
override = R_DS;
gen_op_movl_A0_reg(R_ESI);
gen_op_andl_A0_ffff();
- gen_op_addl_A0_seg(override);
+ gen_op_addl_A0_seg(s, override);
}
}
@@ -638,7 +645,7 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s)
} else {
gen_op_movl_A0_reg(R_EDI);
gen_op_andl_A0_ffff();
- gen_op_addl_A0_seg(R_ES);
+ gen_op_addl_A0_seg(s, R_ES);
}
}
@@ -2063,7 +2070,7 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int
*reg_ptr, int *offset_
} else
#endif
{
- gen_op_addl_A0_seg(override);
+ gen_op_addl_A0_seg(s, override);
}
}
} else {
@@ -2130,7 +2137,7 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int
*reg_ptr, int *offset_
else
override = R_DS;
}
- gen_op_addl_A0_seg(override);
+ gen_op_addl_A0_seg(s, override);
}
}
@@ -2207,7 +2214,7 @@ static void gen_add_A0_ds_seg(DisasContext *s)
} else
#endif
{
- gen_op_addl_A0_seg(override);
+ gen_op_addl_A0_seg(s, override);
}
}
}
@@ -2460,12 +2467,12 @@ static void gen_push_T0(DisasContext *s)
if (s->ss32) {
if (s->addseg) {
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- gen_op_addl_A0_seg(R_SS);
+ gen_op_addl_A0_seg(s, R_SS);
}
} else {
gen_op_andl_A0_ffff();
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- gen_op_addl_A0_seg(R_SS);
+ gen_op_addl_A0_seg(s, R_SS);
}
gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
if (s->ss32 && !s->addseg)
@@ -2500,11 +2507,11 @@ static void gen_push_T1(DisasContext *s)
gen_op_addl_A0_im(-4);
if (s->ss32) {
if (s->addseg) {
- gen_op_addl_A0_seg(R_SS);
+ gen_op_addl_A0_seg(s, R_SS);
}
} else {
gen_op_andl_A0_ffff();
- gen_op_addl_A0_seg(R_SS);
+ gen_op_addl_A0_seg(s, R_SS);
}
gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
@@ -2528,10 +2535,10 @@ static void gen_pop_T0(DisasContext *s)
gen_op_movl_A0_reg(R_ESP);
if (s->ss32) {
if (s->addseg)
- gen_op_addl_A0_seg(R_SS);
+ gen_op_addl_A0_seg(s, R_SS);
} else {
gen_op_andl_A0_ffff();
- gen_op_addl_A0_seg(R_SS);
+ gen_op_addl_A0_seg(s, R_SS);
}
gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
}
@@ -2556,7 +2563,7 @@ static void gen_stack_A0(DisasContext *s)
gen_op_andl_A0_ffff();
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
- gen_op_addl_A0_seg(R_SS);
+ gen_op_addl_A0_seg(s, R_SS);
}
/* NOTE: wrap around in 16 bit not fully handled */
@@ -2569,7 +2576,7 @@ static void gen_pusha(DisasContext *s)
gen_op_andl_A0_ffff();
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
- gen_op_addl_A0_seg(R_SS);
+ gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
@@ -2588,7 +2595,7 @@ static void gen_popa(DisasContext *s)
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
if (s->addseg)
- gen_op_addl_A0_seg(R_SS);
+ gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
@@ -2638,7 +2645,7 @@ static void gen_enter(DisasContext *s, int esp_addend,
int level)
gen_op_andl_A0_ffff();
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
- gen_op_addl_A0_seg(R_SS);
+ gen_op_addl_A0_seg(s, R_SS);
/* push bp */
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
gen_op_st_T0_A0(ot + s->mem_index);
--
1.7.10.4
- [Qemu-devel] [PATCH 21/60] vnc: fix "info vnc" with "-vnc ..., reverse=on", (continued)
- [Qemu-devel] [PATCH 21/60] vnc: fix "info vnc" with "-vnc ..., reverse=on", Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 38/60] xhci: fix usb name in caps, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 26/60] target-i386: Allow tsc-frequency to be larger then 2.147G, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 57/60] buffered_file: do not send more than s->bytes_xfer bytes per tick, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 42/60] target-mips: fix wrong microMIPS opcode encoding, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 11/60] net: add -netdev options to man page, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 30/60] MIPS: Correct FCR0 initialization, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 25/60] hw: Fix return value check for bdrv_read, bdrv_write, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 58/60] qxl: save qemu_create_displaysurface_from result, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 50/60] slirp: Don't crash on packets from 0.0.0.0/8., Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 27/60] x86: Fixed incorrect segment base address addition in 64-bits mode,
Michael Tokarev <=
- [Qemu-devel] [PATCH 49/60] tap: reset vnet header size on open, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 18/60] e1000: flush queue whenever can_receive can go from false to true, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 19/60] fix entry pointer for ELF kernels loaded with -kernel option, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 31/60] linux-user: fix emulation of getdents, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 12/60] intel_hda: do not call msi_reset when only device state needs resetting, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 44/60] qcow2: Fix refcount table size calculation, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 43/60] qcow2: Fix avail_sectors in cluster allocation code, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 13/60] usb-audio: fix usb version, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 14/60] fpu/softfloat.c: Return correctly signed values from uint64_to_float32, Michael Tokarev, 2013/02/04
- [Qemu-devel] [PATCH 40/60] nbd: fixes to read-only handling, Michael Tokarev, 2013/02/04