Re: [Qemu-devel] [PATCH 46/57] target-i386: Implement ANDN

[Andreas Färber]

Am 24.01.2013 05:03, schrieb Richard Henderson:
> As this is the first of the BMI insns to be implemented,
> this carries quite a bit more baggage than normal.
> 
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target-i386/cpu.c       | 10 +++++-----
>  target-i386/translate.c | 19 +++++++++++++++++--
>  2 files changed, 22 insertions(+), 7 deletions(-)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 776b670..30893b6 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -399,12 +399,12 @@ typedef struct x86_def_t {
>  #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
>            CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
>  #define TCG_SVM_FEATURES 0
> -#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
> +#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
> +          CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2)
>            /* missing:
> -          CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_BMI1, CPUID_7_0_EBX_HLE,
> -          CPUID_7_0_EBX_AVX2, CPUID_7_0_EBX_BMI2, CPUID_7_0_EBX_ERMS,
> -          CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED,
> -          CPUID_7_0_EBX_ADX */
> +          CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
> +          CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
> +          CPUID_7_0_EBX_RDSEED, CPUID_7_0_EBX_ADX */
>  
>  /* maintains list of cpu model definitions
>   */

Note this will conflict with the upcoming 1.4 qom-cpu pull, which drops
the duplicate list built from the array.

Andreas

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