Re: [Qemu-devel] [RFC PATCH] PIIX: reset the VM when the Reset Control Register's RCPU bit gets set

[Laszlo Ersek]

Hi,

On 01/09/13 22:01, Blue Swirl wrote:
> On Tue, Jan 8, 2013 at 9:44 PM, Laszlo Ersek <address@hidden> wrote:

>> +static void i440fx_host_config_write(void *opaque, hwaddr addr,
>> +                                     uint64_t val, unsigned len)
>> +{
>> +    if (addr == 1 && len == 1) {
>> +        if (val & 4) {
>> +            qemu_system_reset_request();
>> +        }
>> +        return;
>> +    }
>> +    pci_host_conf_le_ops.write(opaque, addr, val, len);
>> +}
>> +
>> +static MemoryRegionOps i440fx_host_conf_ops = {
>> +    .read       = NULL,
>> +    .write      = i440fx_host_config_write,
>> +    .endianness = DEVICE_LITTLE_ENDIAN
>> +};
>> +
>>  static int i440fx_pcihost_initfn(SysBusDevice *dev)
>>  {
>>      PCIHostState *s = PCI_HOST_BRIDGE(dev);
>>
>> -    memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
>> +    i440fx_host_conf_ops.read = pci_host_conf_le_ops.read;
> 
> It would be cleaner to introduce a new memory region (without this
> copying) which passes 0xcf8 and 0xcfc to standard PCI host but catches
> accesses to 0xcf9. This may mean that pci_host_config_{read,write}
> will need to be exposed.

Do you mean:

(1) introducing the new "i440fx_host_conf_ops" struct-of-funcptrs with
detached functions (that is, duplicating the guts of
pci_host_config_{read,write} and modifying them, and then registering
s->conf_mem with this "i440fx_host_conf_ops"; or

(2) leaving s->conf_mem as-is, and introducing a sub-region just for
port 0xcf9, with higher visibility priority?

(I don't feel confident about (2), and based on "docs/memory.txt" I
thought that overlapping regions had not been invented for this purpose.)

IOW, are you OK with the explicit offset + access-width based check,
just organized differently, or are you proposing a one-byte-wide subregion?

Thanks!
Laszlo