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[Qemu-devel] [PATCH 5/6] hw/arm_gic: fix target CPUs affected by set ena
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 5/6] hw/arm_gic: fix target CPUs affected by set enable/pending ops |
Date: |
Tue, 11 Dec 2012 15:22:39 +0000 |
From: Daniel Sangorrin <address@hidden>
Fix a bug on the ARM GIC model where interrupts are not
set pending on the correct target CPUs when they are
triggered by writes to the Interrupt Set Enable or
Set Pending registers.
Signed-off-by: Daniel Sangorrin <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm_gic.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 672d539..8d769de 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -374,7 +374,8 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
value = 0xff;
for (i = 0; i < 8; i++) {
if (value & (1 << i)) {
- int mask = (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq);
+ int mask =
+ (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i);
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
if (!GIC_TEST_ENABLED(irq + i, cm)) {
@@ -417,7 +418,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
for (i = 0; i < 8; i++) {
if (value & (1 << i)) {
- GIC_SET_PENDING(irq + i, GIC_TARGET(irq));
+ GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i));
}
}
} else if (offset < 0x300) {
--
1.7.9.5
- [Qemu-devel] [PULL 0/6] arm-devs queue, Peter Maydell, 2012/12/11
- [Qemu-devel] [PATCH 1/6] hw/arm_boot, exynos4210, highbank: Fix secondary boot GIC init, Peter Maydell, 2012/12/11
- [Qemu-devel] [PATCH 6/6] exynos4210/mct: Avoid infinite loop on non incremental timers, Peter Maydell, 2012/12/11
- [Qemu-devel] [PATCH 4/6] xilinx_zynq: Add one variable to avoid overwriting QSPI bus, Peter Maydell, 2012/12/11
- [Qemu-devel] [PATCH 5/6] hw/arm_gic: fix target CPUs affected by set enable/pending ops,
Peter Maydell <=
- [Qemu-devel] [PATCH 2/6] hw/arm_gic: Fix comparison with priority mask register, Peter Maydell, 2012/12/11
- [Qemu-devel] [PATCH 3/6] hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs, Peter Maydell, 2012/12/11