[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 11/18] acpi: cleanup ich9 memory region
From: |
Gerd Hoffmann |
Subject: |
[Qemu-devel] [PATCH v2 11/18] acpi: cleanup ich9 memory region |
Date: |
Tue, 27 Nov 2012 09:59:21 +0100 |
Nothing left to do, everything handled by subregions,
we can zap the reaw/write handlers now.
Signed-off-by: Gerd Hoffmann <address@hidden>
---
hw/acpi_ich9.c | 125 +-------------------------------------------------------
1 files changed, 1 insertions(+), 124 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index 0ed17da..db0d7a5 100644
--- a/hw/acpi_ich9.c
+++ b/hw/acpi_ich9.c
@@ -42,10 +42,6 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
#define ICH9_DEBUG(fmt, ...) do { } while (0)
#endif
-static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
- uint32_t val);
-static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
-
static void pm_update_sci(ICH9LPCPMRegs *pm)
{
int sci_level, pm1a_sts;
@@ -71,125 +67,6 @@ static void ich9_pm_update_sci_fn(ACPIREGS *regs)
pm_update_sci(pm);
}
-static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
-{
- switch (addr & ICH9_PMIO_MASK) {
- default:
- break;
- }
-
- ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
-}
-
-static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
-{
- uint32_t val = 0;
-
- switch (addr & ICH9_PMIO_MASK) {
- default:
- val = 0;
- break;
- }
- ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
- return val;
-}
-
-static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
-{
- switch (addr & ICH9_PMIO_MASK) {
- default:
- pm_ioport_write_fallback(opaque, addr, 2, val);
- break;
- }
- ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
-}
-
-static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
-{
- uint32_t val;
-
- switch (addr & ICH9_PMIO_MASK) {
- default:
- val = pm_ioport_read_fallback(opaque, addr, 2);
- break;
- }
- ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
- return val;
-}
-
-static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
-{
- switch (addr & ICH9_PMIO_MASK) {
- default:
- pm_ioport_write_fallback(opaque, addr, 4, val);
- break;
- }
- ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
-}
-
-static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
-{
- uint32_t val;
-
- switch (addr & ICH9_PMIO_MASK) {
- default:
- val = pm_ioport_read_fallback(opaque, addr, 4);
- break;
- }
- ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
- return val;
-}
-
-static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
- uint32_t val)
- {
- int subsize = (len == 4) ? 2 : 1;
- IOPortWriteFunc *ioport_write =
- (subsize == 2) ? pm_ioport_writew : pm_ioport_writeb;
-
- int i;
-
- for (i = 0; i < len; i += subsize) {
- ioport_write(opaque, addr, val);
- val >>= 8 * subsize;
- }
-}
-
-static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
-{
- int subsize = (len == 4) ? 2 : 1;
- IOPortReadFunc *ioport_read =
- (subsize == 2) ? pm_ioport_readw : pm_ioport_readb;
-
- uint32_t val;
- int i;
-
- val = 0;
- for (i = 0; i < len; i += subsize) {
- val <<= 8 * subsize;
- val |= ioport_read(opaque, addr);
- }
-
- return val;
-}
-
-static const MemoryRegionOps pm_io_ops = {
- .old_portio = (MemoryRegionPortio[]) {
- { .offset = 0, .len = ICH9_PMIO_SIZE, .size = 1,
- .read = pm_ioport_readb, .write = pm_ioport_writeb },
- { .offset = 0, .len = ICH9_PMIO_SIZE, .size = 2,
- .read = pm_ioport_readw, .write = pm_ioport_writew },
- { .offset = 0, .len = ICH9_PMIO_SIZE, .size = 4,
- .read = pm_ioport_readl, .write = pm_ioport_writel },
- PORTIO_END_OF_LIST(),
- },
- .valid.min_access_size = 1,
- .valid.max_access_size = 4,
- .impl.min_access_size = 1,
- .impl.max_access_size = 4,
- .endianness = DEVICE_LITTLE_ENDIAN,
-};
-
static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
{
ICH9LPCPMRegs *pm = opaque;
@@ -326,7 +203,7 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
{
- memory_region_init_io(&pm->io, &pm_io_ops, pm, "ich9-pm", ICH9_PMIO_SIZE);
+ memory_region_init(&pm->io, "ich9-pm", ICH9_PMIO_SIZE);
memory_region_set_enabled(&pm->io, false);
memory_region_add_subregion(get_system_io(), 0, &pm->io);
--
1.7.1
- [Qemu-devel] [PATCH v2 18/18] acpi: drop debug port, (continued)
- [Qemu-devel] [PATCH v2 18/18] acpi: drop debug port, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 08/18] acpi: cleanup vt82c686 memory region, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 16/18] apci: switch piix4 pci hotplug to memory api, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 15/18] acpi: remove acpi_gpe_blk, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 14/18] apci: switch piix4 gpe to memory api, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 01/18] apci: switch piix4 to memory api, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 12/18] acpi: switch smbus to memory api, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 10/18] apci: switch ich9 smi to memory api, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 06/18] apci: switch evt to memory api, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 04/18] apci: switch timer to memory api, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 11/18] acpi: cleanup ich9 memory region,
Gerd Hoffmann <=
- [Qemu-devel] [PATCH v2 05/18] apci: switch cnt to memory api, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 17/18] q35: update lpc pci config space according to configured devices, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 13/18] acpi: fix piix4 smbus mapping, Gerd Hoffmann, 2012/11/27
- [Qemu-devel] [PATCH v2 09/18] apci: switch ich9 gpe to memory api, Gerd Hoffmann, 2012/11/27