Re: [Qemu-devel] [PATCH 1/7] target-mips: fix DSP loads with rd = 0

[Johnson, Eric]

> -----Original Message-----
> From: address@hidden [mailto:qemu-devel-
> address@hidden On Behalf Of Aurelien Jarno
> Sent: Friday, November 16, 2012 3:04 AM
> To: address@hidden
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH 1/7] target-mips: fix DSP loads with rd = 0
> 
> When rd is 0, which still need to do the actually load to possibly
> generate a TLB exception.
> 
> Signed-off-by: Aurelien Jarno <address@hidden>
> ---
>  target-mips/translate.c |    5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 01b48fa..c3e00c5 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -12631,11 +12631,6 @@ static void gen_mipsdsp_ld(CPUMIPSState *env,
> DisasContext *ctx, uint32_t opc,
>      const char *opn = "ldx";
>      TCGv t0;
> 
> -    if (rd == 0) {
> -        MIPS_DEBUG("NOP");
> -        return;
> -    }
> -
>      check_dsp(ctx);
>      t0 = tcg_temp_new();
> 
> --
> 1.7.10.4
> 

Reviewed-by: Eric Johnson <address@hidden>