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[Qemu-devel] [PATCH v4 03/14] pc_piix: Move kvm irq routing functions ou
From: |
Jason Baron |
Subject: |
[Qemu-devel] [PATCH v4 03/14] pc_piix: Move kvm irq routing functions out of pc_piix.c |
Date: |
Wed, 14 Nov 2012 15:54:02 -0500 |
From: Jason Baron <address@hidden>
Rename: kvm_piix3_gsi_handlei() -> kvm_pc_gsi_handler()
kvm_piix3_setup_irq_routing() -> kvm_pc_setup_irq_routing()
This is in preparation for other users, namely q35 at this time.
Signed-off-by: Jason Baron <address@hidden>
---
hw/kvm/ioapic.c | 40 ++++++++++++++++++++++++++++++++++++++++
hw/pc_piix.c | 45 ++-------------------------------------------
kvm.h | 2 ++
3 files changed, 44 insertions(+), 43 deletions(-)
diff --git a/hw/kvm/ioapic.c b/hw/kvm/ioapic.c
index 6c3b8fe..f95c157 100644
--- a/hw/kvm/ioapic.c
+++ b/hw/kvm/ioapic.c
@@ -15,6 +15,46 @@
#include "hw/apic_internal.h"
#include "kvm.h"
+/* PC Utility function */
+void kvm_pc_setup_irq_routing(bool pci_enabled)
+{
+ KVMState *s = kvm_state;
+ int i;
+
+ if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
+ for (i = 0; i < 8; ++i) {
+ if (i == 2) {
+ continue;
+ }
+ kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i);
+ }
+ for (i = 8; i < 16; ++i) {
+ kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
+ }
+ if (pci_enabled) {
+ for (i = 0; i < 24; ++i) {
+ if (i == 0) {
+ kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
+ } else if (i != 2) {
+ kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i);
+ }
+ }
+ }
+ }
+}
+
+void kvm_pc_gsi_handler(void *opaque, int n, int level)
+{
+ GSIState *s = opaque;
+
+ if (n < ISA_NUM_IRQS) {
+ /* Kernel will forward to both PIC and IOAPIC */
+ qemu_set_irq(s->i8259_irq[n], level);
+ } else {
+ qemu_set_irq(s->ioapic_irq[n], level);
+ }
+}
+
typedef struct KVMIOAPICState KVMIOAPICState;
struct KVMIOAPICState {
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index e460799..aa3e7f4 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -54,47 +54,6 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
-static void kvm_piix3_setup_irq_routing(bool pci_enabled)
-{
-#ifdef CONFIG_KVM
- KVMState *s = kvm_state;
- int i;
-
- if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
- for (i = 0; i < 8; ++i) {
- if (i == 2) {
- continue;
- }
- kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i);
- }
- for (i = 8; i < 16; ++i) {
- kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
- }
- if (pci_enabled) {
- for (i = 0; i < 24; ++i) {
- if (i == 0) {
- kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
- } else if (i != 2) {
- kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i);
- }
- }
- }
- }
-#endif /* CONFIG_KVM */
-}
-
-static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
-{
- GSIState *s = opaque;
-
- if (n < ISA_NUM_IRQS) {
- /* Kernel will forward to both PIC and IOAPIC */
- qemu_set_irq(s->i8259_irq[n], level);
- } else {
- qemu_set_irq(s->ioapic_irq[n], level);
- }
-}
-
/* PC hardware initialisation */
static void pc_init1(MemoryRegion *system_memory,
MemoryRegion *system_io,
@@ -160,8 +119,8 @@ static void pc_init1(MemoryRegion *system_memory,
gsi_state = g_malloc0(sizeof(*gsi_state));
if (kvm_irqchip_in_kernel()) {
- kvm_piix3_setup_irq_routing(pci_enabled);
- gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
+ kvm_pc_setup_irq_routing(pci_enabled);
+ gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
GSI_NUM_PINS);
} else {
gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
diff --git a/kvm.h b/kvm.h
index 1e7f244..72d866a 100644
--- a/kvm.h
+++ b/kvm.h
@@ -275,4 +275,6 @@ void kvm_irqchip_release_virq(KVMState *s, int virq);
int kvm_irqchip_add_irqfd_notifier(KVMState *s, EventNotifier *n, int virq);
int kvm_irqchip_remove_irqfd_notifier(KVMState *s, EventNotifier *n, int virq);
+void kvm_pc_gsi_handler(void *opaque, int n, int level);
+void kvm_pc_setup_irq_routing(bool pci_enabled);
#endif
--
1.7.1
- [Qemu-devel] [PATCH v4 00/14] Add Q35 base support, Jason Baron, 2012/11/14
- [Qemu-devel] [PATCH v4 01/14] pc, pc_piix: split out pc nic initialization, Jason Baron, 2012/11/14
- [Qemu-devel] [PATCH v4 02/14] pc: Move ioapic_init() from pc_piix.c to pc.c, Jason Baron, 2012/11/14
- [Qemu-devel] [PATCH v4 03/14] pc_piix: Move kvm irq routing functions out of pc_piix.c,
Jason Baron <=
- [Qemu-devel] [PATCH v4 04/14] pc/piix_pci: factor out smram/pam logic, Jason Baron, 2012/11/14
- [Qemu-devel] [PATCH v4 05/14] ich9: Add acpi support and definitions, Jason Baron, 2012/11/14
- [Qemu-devel] [PATCH v4 06/14] ich9: Add the lpc chip, Jason Baron, 2012/11/14
- [Qemu-devel] [PATCH v4 07/14] ich9: Add smbus, Jason Baron, 2012/11/14
- [Qemu-devel] [PATCH v4 08/14] q35: Introduce q35 pc based chipset emulator, Jason Baron, 2012/11/14
- [Qemu-devel] [PATCH v4 09/14] ich9: Add i82801b11 dmi-to-pci bridge, Jason Baron, 2012/11/14
- [Qemu-devel] [PATCH v4 10/14] q35: Suppress SMM BIOS initialization under KVM, Jason Baron, 2012/11/14
- [Qemu-devel] [PATCH v4 11/14] q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic, Jason Baron, 2012/11/14